Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-03-23
2001-01-23
Fears, Terrell W. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S230050
Reexamination Certificate
active
06178126
ABSTRACT:
BACKGROUND OF THE INVENTION
CMOS technology has evolved such that the computer market has rapidly opened to a wide range of consumers. Today, multi-media requires at least a 64 MB, and preferably even a 128 MB random access memory (RAM), which increases the relative cost of the memory system within the computer. In the near future, it is likely that 256 MB and 512 MB computers will become commonplace, which suggests a potential strong demand for 256 Mb RAMs and beyond. Still in the development stage, RAMs in the Gigabit range are already under way. As RAM density and lithographic difficulties increase, it is more difficult to obtain RAMs which are fully functional. Process and design engineers are continuously attempting to reduce and, ultimately, eliminate mask defects.
It has long been practiced in the art creating redundant circuits which can substitute failing circuits during a repair operation, wherein the process of repairing involves creating and/or destructing connections to the RAM. Most RAMs are organized as 2-dimensional arrays of rows and columns. Redundant circuits usually take the form of spare rows and columns and switchable connections known as fuses. An approach typically used for repairing a RAM is known as redundancy replacement, wherein a redundancy address for replacing a faulty element is identified at the device level and programmed by blowing laser fuses or electrically programmable fuses. Redundancy replacement with laser fuses is the most commonly used approach to improve memory device yield, the details of which are well described in the article, T. Kirihata et. al., “Fault-Tolerant Designs for 256 Mb DRAM,” IEEE Solid-State Circuits, Vol. 31, No. 4, April 1996, pp. 558-556. An on-chip programming method and the detailed of the embodiment with the electrically programmable fuses are well discussed in U.S. patent application Ser. No. 09/512,922, entitled “Method of Addressing Electrical fuses”.
Typical electric systems, such as personal computers, employ a plurality of RAMs to embody a main memory of adequate density (i.e., 128 MB) coupled to data ports (i.e., 64 bits). More particularly, the main memory is configured by arranging a plurality of Dual-In line-Memory-Modules (DIMM), each consisting of a plurality of RAMs. When the RAMs are arranged in a DIMM configuration, programming a redundancy address in at least two of the memory devices is required to perform a repair at the DIMM or at system level.
FIG. 1
shows a simplified version of a standard DIMM (
100
). The DIMM ports consist of a clock port (CLK), control ports ({overscore (CS)}, {overscore (RAS)}, {overscore (CAS)}, {overscore (WE)}), address ports (ADRs), and 64 data ports (DQ<
0
:
63
>) coupled to a system memory bus. Eight RAMs (RAM 0-7), each having 8 RAM data ports (i.e., DQ<
0
:
7
> for RAM0) are arranged within DIMM (
100
), wherein the clock (CLK), address bus (a plurality of address lines ADRs), and control bus ({overscore (CS)}, {overscore (RAS)}, {overscore (CAS)}, {overscore (WE)}) of all the RAMs 0-7 are interconnected and coupled to the corresponding DIMM ports. DQ<
0
:
63
> are preferably arranged in 8 DQ groups, each having 8 data ports coupled to appropriate RAM data ports in the corresponding RAMs. More particularly, DQ<
0
:
7
>, DQ<
8
:
15
>, DQ<
16
:
23
>, DQ<
24
:
31
>, DQ<
32
:
39
>,DQ<
40
:
47
>, DQ<
48
:
55
>, and DQ<
56
:
63
> are coupled to RAM0, RAM1, RAM2, RAM3, RAM4, RAM5, RAM6, and RAM7, respectively. In a typical electric system, a memory controller regulates the common control buses ({overscore (CS)}, {overscore (RAS)}, {overscore (CAS)}, {overscore (WE)}) and address buses (ADRs) such that a 64 bit data communication between all RAMs in the DIMM and the memory controller is realized by way of the system memory data bus (DQ<
0
:
63
>). Thus, all the memories in the DIMM are accessed (either read from or written to) in parallel with the common control and address bus.
In order to repair a fault in a plurality of RAMs within a plurality of DIMMs in an electric system, it is necessary to identify one DIMM of the plurality of DIMMs, the pertinent RAMs within the identified DIMM, and a redundancy address within the identified RAM. By way of example, U.S. Pat. No. 5,764,574 proposes the use of a RAM data port for programming a redundancy address within the RAM. The data ports of the RAMs in the DIMM are not coupled to the same DIMM data ports. This allows a redundancy address in each RAM to be programmed independently through the corresponding DIMM data ports. However, in an actual electric system, there exists a variety of RAMs which contain a different number of the data ports. It is highly unlikely to have a similar redundancy architecture which is applicable to all RAM configurations. These considerations cause a potential difficulty when using the prior art. Moreover, it is undesirable to enforce using a redundancy address programming protocol without considering the system standard protocol, particularly since it is very important to follow existing electric standards. The most important issue is to follow a fully compatible protocol for addressing the memory cells and programming a redundancy address. This is because the redundancy address to be programmed is the address which is inoperative when the protocol is applied. Until now, this problem was not fully considered. Therefore, today, when a RAM fails in the field, (i.e., installed in an electric system), at least one DIMM having the defective RAM or all of the RAMs must be replaced. Solving this problem necessitates introducing new techniques that guarantee the repair of RAMs within a DIMM or electric system notwithstanding the added complexity to the design and manufacture.
OBJECTS OF THE INVENTION
Accordingly, it is an object of the invention to provide a method of identifying and programming a redundancy address in a plurality of RAMs arranged in a dual-in line-memory- module (DIMM) configuration or within a plurality of DIMMs forming an electric system to perform a repair at system level that guarantees full functionality of the DIMM and of the electric system.
It is another object of the invention to have a memory controller identify the memory data port organization and specific system information within each RAM, whether it is arranged in a DIMM or in an electric system, after that the system has been fully configured.
It is a further object of the invention to provide a protocol to perform a field repair of RAMs arranged in a memory module or within an electric system.
It is yet another object of the invention to use an existing protocol with a minimal modification to generate a field repair of RAMs arranged in a memory module or an electric system.
It is still a further object of the invention to use a microprocessor for testing a plurality of RAMs in an electric system, analyze the redundancy addresses, and program a redundancy address to effect a field repair.
It is yet a further object of the invention to provide a method to store an electric system information into a RAM arranged in the electric system, the information of which can be read out after the RAM is disassembled for a field problem analysis.
SUMMARY OF THE INVENTION
In one aspect of the invention, there is provided a plurality of RAMs, each consisting of a plurality of memory cells arranged in a matrix. The RAMs are preferably arranged in a plurality of dual-in line-memory modules (DIMMs) within an electric system, wherein a defective memory cell address (redundancy address) in any RAMs can be identified, while following existing RAM standard protocols with minimal modifications. More particularly, a defective memory cell within a plurality of RAMs in a plurality of DlMMs is identified by at least two protocols available in the electric system. The first protocol is a mode register set command (or extended mode register set command) which selects a DIMM by way of a chip select signal ({overscore (CS)}) and designates a RAM by way of at least one data port
Coteus Paul W.
Kirihata Toshiaki
Maule Warren E.
Tomashot Steven
Fears Terrell W.
International Business Machines - Corporation
Schnurmann H. Daniel
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