Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2005-12-27
2005-12-27
Le, Dieu-Minh (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S710000
Reexamination Certificate
active
06981175
ABSTRACT:
A memory includes: a memory array having a plurality of storage elements; a plurality of replacement storage elements; a plurality of address fuse units, each having a plurality of fusible links and being operable to store a replacement address, each replacement address identifying one of the storage elements of the memory array to be replaced by an associated one of the replacement storage elements and forming a respective 2mbit row or 2nbit column of a fuse array; a vector generator operable to produce a 2nbit row vector based on the rows of the fuse array and to produce a 2mbit column vector based on the columns of the fuse array; and a compression unit operable to produce a row checksum from the row vector and to produce a column checksum from the column vector.
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Moore Philip
Vollrath Joerg
Brinks Hofer Gilson & Lione
Infineon - Technologies AG
Le Dieu-Minh
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