Memory and a data processor including a memory

Details Memory and a data processor including a memory Memory and a data processor including a memory

1998-02-06

2002-05-07

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C712S037000

Reexamination Certificate

active

06385689

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a memory and to a programmable data processor including such a memory.
BACKGROUND OF THE INVENTION
Data processors, such as microcontrollers typically include some or all of the following types of nonvolatile memory blocks:
Code memory—this is usually implemented in ROM, EPROM on in flash electrically erasable programmable read only memory (EEPROM). The term “flash” denotes that large blocks of memory are erasable simultaneously, since each cell is a single transistor.
User non-volatile data memory, usually two transistor EEPROM, thereby allowing single word (usually one byte) erase and programming.
Security—This is typically a separate block of memory bits which control access rights to the other blocks. Some levels of security allow the program code to be read back, but not to be erased or altered. Other levels of security inhibit reading of the program code as well.
Bootstrap memory—This is a “hidden” memory which usually does not appear on the data sheet and is not accessible by the user. The bootstrap memory includes code which is executed by the microcontroller as part of its power up sequence and also contains instructions for initialisation of registers, controlling emulation and data transfer, such as the instructions for down loading new program code. Bootstrap memory is usually implemented in Read only memory, ROM, and a significant disadvantage of this is that the instruction code is fabricated into the ROM during manufacture, thus making it very difficult to ensure that the code is correct during design of the data processor, and also meaning that changes in the code require the production of a new topography and consequently new masks are required to implement a change to just one byte of the bootstrap code.
The differing use requirements placed upon these various blocks of memory have caused manufacturers of devices such as microcontrollers, digital signal processors or other data processors to implement these different memories as physically different blocks. For example, the ROM bootstrap and EPROM program memory cannot easily be merged due to different cell sizes and layout, or one memory may be in low voltage read out while the other is simultaneously in a high voltage erase condition. Furthermore, since flash EEPROM is often the memory type of choice for code memory, the fact that large blocks of flash EEPROM are erased simultaneously makes this type of memory unsuitable for use as a non-volatile data memory since this inherently requires the ability to modify single bytes at a time.
The use of separate memory blocks does have a significant disadvantage in that space on the silicon is wasted in duplication of features common to each memory, such as address decoders, sense amplifiers, and in the case of EEPROM, charge pumps and high voltage circuitry for the erase and programming operations.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, there is provided a data processor comprising at least two reprogrammed non-volatile memories selected from a list comprising a bootstrap memory, a program memory and a data memory, wherein the at least two memories are of the same construction.
Preferably the memories are flash EEPROM. Flash EEPROM is a relatively compact memory type and the use of such a memory is an efficient use of space on the semiconductor used to form the integrated circuit. The memories may comprise an array of memory elements formed by split gate transistors having first, second and third terminals, the transistors being arranged in a matrix which advantageously has orthogonal axes, such as rows and columns such that the first terminals of transistors in a row are connected to a first shared conductor, and such that the second terminals of transistors in a column are connected to a second shared conductor.
Advantageously the rows of transistors are grouped into pairs with the third terminals of the transistors in the pair of rows being connected to a third shared conductor. Such an arrangement reduces the space required by the array of memory cells and associated addressing and controlling circuitry compared to a similar memory wherein the transistors are not grouped into pairs. Advantageously the first terminals are gate terminals, the second terminals are drain terminals and the third terminals are source terminals.
In the EEPROM memory, memory elements may be erasable by connecting the first shared conductor of a row to a first voltage and the second and third conductors to a second voltage less than the first voltage. For example, the gate electrode may be connected to a +15 volt supply whereas the drain and source may be connected to ground. Where the sources of transistors in paired rows are connected to a common node, the gate electrodes of the transistors in the paired rows are connected to the first voltage during an erase such that both rows in a pair are erased simultaneously. This ensures that disturbance between the rows is effectively eliminated.
Preferably the data processor further comprises a memory controller in association with a data memory arranged, when a row of the memory is to be updated, to read the contents of the entire row into a register such that the data stored in the row is held within the register when the row is erased. The contents of register can be altered and then the register can be used to reprogram the erased row. Advantageously the register is at least one byte wide and individual bytes within the register can be changed without changing any other byte. The data memory may also be implemented with paired rows of memory cells sharing a source node. In such an arrangement registers must be provided for each row in the pair.
Preferably the bootstrap memory is programmable. This alleviates the design problems associated with correctly writing the bootstrap code before mask fabrication for the data processor. It also enables code upgrades to be released should this be desirable, for example to cope with changes in associated components or technological upgrades.
Preferably the at least two memories share an address decoder. This reduces or alleviates the need to duplicate components such as address decoders, sense amplifiers and charge pumps. Advantageously the bootstrap memory is an allocated area within a larger memory block, the remainder of the block being used as a program memory.
Preferably the data processor further comprises a memory controller. The memory controller handles the sequences of events necessary to erase or program the memory. Advantageously the memory controller is implemented as a state machine which is responsive to a system clock. Thus the operations of the state machine may be synchronised to the system clock.
Preferably the state machine is arranged to control the switch on and switch off times of an erase pulse which is supplied to the gates of selected rows of transistors in order to erase the rows. The state machine may include at least one programmable register for controlling the commencement of and duration of the erase pulse.
Advantageously the state machine controls the duration of a first write pulse applied to the gate of a selected transistor during the writing of a memory cell. The state machine may also control the duration of a second write pulse applied to the source of a selected transistor during the writing of a memory cell. The state machine may include one or more programmable registers for adjustably controlling the commencement and duration of the first and/or second pulse.
Advantageously the data processor is placed into an idle mode before the state machine commences control of a memory erase or write operation. The data processor returns from its idle mode after the state machine has completed its erase or write operations. The data processor can predict the time (i.e. the number of clock cycles) for the state machine to complete an erase or write sequence. The data processor enters the idle mode for at least the number of clock cycles required by the state machine and, once t

Affiliated with

Also associated with

Rating

Memory and a data processor including a memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory and a data processor including a memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory and a data processor including a memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2905349