Electrical computers and digital processing systems: memory – Address formation
Reexamination Certificate
1998-07-22
2001-03-13
Chan, Eddie P. (Department: 2751)
Electrical computers and digital processing systems: memory
Address formation
C711S211000, C711S220000, C365S189020, C365S230010, C365S230020, C710S120000, C710S120000, C710S120000
Reexamination Certificate
active
06202140
ABSTRACT:
FIELD OF THE INVENTION
This invention is in the field of memory addressing systems and methods therefor, and more particularly, is a system and method for decreasing the PIN count of a companion chip while increasing the address space and memory map flexibility between the CPU, memory and other coupled peripheral devices.
BACKGROUND OF THE INVENTION
Architecture
In a traditional computer system, the Central Processing Unit (CPU) will generate an address on an address bus and then read or write data on a separate data bus. This is denoted as a parallel bus architecture and is depicted in
FIG. 3. A
control bus from the CPU runs parallel to the address bus and the data bus to provide signals for such things as ADDRESS_VALID and control whether the cycle is a READ or a WRITE operation. The control bus and data bus then typically connect to a controller, or companion chip, which is designed to communicate to devices such as ROM, SRAM, DRAM or other peripherals such as graphics cards and modems. A companion chip is required in most systems because even though a CPU can communicate with many different devices, it cannot do so well, nor can a CPU communicate with all types of devices. A typical timing diagram for a parallel bus architecture is shown in FIG.
1
. If the CPU can directly support ROM accesses, (for instance the Pentium can not), the parallel bus architecture, as shown in
FIG. 3
, can significantly reduce the size of the companion chip because an address bus does not need to be routed via a companion chip as is required in a multiplexed system. The parallel bus method also results in a flexibility in designing how much ROM address space can be attached to the CPU.
The disadvantage to a parallel bus architecture is a reduction of flexibility in the memory map. This reduction in this configuration occurs because it is not possible for the companion chip to see the addresses when the CPU communicates with the ROM thus resulting in a loss of the ability to control how far into ROM space the CPU is addressing.
In an alternative design, some CPUs have their architecture designed to eliminate the separate address bus in order to reduce the PIN count. This method is attractive due to the smaller numbers of PINs which translate directly to a less expensive device due to cheaper package, smaller die etc. This alternative design uses a multiplexed address/data bus. The multiplexed address/data bus has multiple cycles with the first cycle being address and command, the second being data. A typical timing diagram for a multiplex bus architecture is shown in
FIG. 2
, and a multiplexed bus architecture is depicted in FIG.
4
. This method has the advantage of a smaller PIN out count from the CPU, and also results in the ability of the companion chip to see the entire address space as the CPU accesses it and can thus use the CPU address space efficiently by allocating it to other devices. For example, if the ROM space is greater than 2 Mbytes in size, but ROM is 2 Mbytes is size, other devices can be mapped at the address 2 MEG+1.
This design also has its disadvantages however. When dealing with devices that cannot operate in a multiplex mode and which require a parallel bus architecture, such as ROM and FLASH memory, the companion chip must now have an address bus included in the package to be able to communicate to the ROM. This results in a larger companion chip die and package size due to the number of PINs required to generate an address bus and the cost per companion chip goes up. For example, 2 Megabytes of ROM, addressed as a byte addressable ROM, requires that 21 PINs be added to the companion chip package, and if an extremely large ROM space existed, such as on the order of 64 MEG, as many as 26 address PINs would need to be added to the companion chip in order to actually address the ROM. An additional drawback to a multiplexed bus architecture is that once the size of the address bus from the companion chip is set, larger address ROMs or devices that would require additional PINs for the increase in the address bus width cannot be used.
A modification to the multiplexed bus design is to add an address bus from the CPU to the ROM, and program the CPU so that when communicating to the ROM, the CPU will not use the multiplex mode, but instead will function in a parallel bus mode. This modification creates a number of its own problems however. As previously discussed, while communicating to the ROM in this mode, the companion chip is not receiving nor decoding the address information. So, again, this results is a loss of having a flexible memory map, thus losing the ability to control how far into ROM space the CPU is addressing.
Therefor, a need existed to provide an improved system and method of addressing memory and other peripheral devices, such as ROM. The improved system and method of addressing memory and other peripheral devices would make it possible for the companion chip to see the addresses when the CPU communicates with the ROM thus resulting in the ability to control how far into ROM space the CPU is addressing. Additionally, a need existed to limit the number of PINs required to be added to a companion chip for the multiplex mode of operation while still providing for an acceptable and flexible address space from a CPU to ROM and other peripheral devices.
SUMMARY OF THE INVENTION
The present invention provides an improved memory addressing system for addressing peripheral devices such as ROM and an approach that makes it possible for the companion chip to see the addresses when the CPU communicates with the ROM.
The present invention further provides a system and method that will limit the number of PINs required to be added to a companion chip for the multiplex mode of operation while still providing for an acceptable flexible address space from a CPU to ROM and other peripheral devices
BRIEF DESCRIPTION
In accordance with one example embodiment of the present invention, an improved memory addressing system comprises a CPU having an address bus and a multiplexed data/address bus, a companion chip, and memory storage. The companion chip is coupled to the multiplexed data/address bus for receiving and for decoding a low order address from the multiplexed data/address bus. The memory storage is coupled to the address bus for receiving a high order address from the address bus, and coupled to the companion chip for receiving the low order address. The companion chip further comprises a data decoding device for decoding data from the multiplexed data/address bus and a FLASH write circuit. The improved memory addressing system further comprises a data bus coupled to the companion chip and to the memory storage for transmission of the data between the companion chip and the memory storage, and a low order address bus coupled to the companion chip and to the memory storage for transmitting the low order address from the companion chip to the memory storage. The memory storage comprises non-volatile memory comprised of ROM or FLASH memory. The CPU further comprises transmitting control circuitry for transmitting information on both of the multiplexed data/address bus and the address bus at substantially the same time. The improved memory addressing system further comprises a low order address bus coupled to the companion chip and to the memory storage for transmitting the low order address from the companion chip to the memory storage.
In accordance with another embodiment of the present invention, an improved memory addressing method is disclosed comprising, the steps of providing a CPU having both an address bus and a multiplexed data/address bus wherein the CPU transmits information on both of the address bus and the multiplexed data/address bus at substantially the same time, providing a companion chip coupled to the multiplexed data/address bus for receiving and for decoding a low order address from the multiplexed data/address bus, and providing memory storage coupled to the address bus for receiving a high order address from the address bus and to the comp
Evoy David
Rose Jerry Michael
Chan Eddie P.
McLean Kimberly
Philips Semiconductor Inc.
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