Memory addressing scheme using partition strides

Details Memory addressing scheme using partition strides Memory addressing scheme using partition strides

2011-01-18

2011-01-18

Tung, Kee M (Department: 2628)

Computer graphics processing and selective visual display system

Computer graphics display memory system

Memory partitioning

C345S540000, C345S571000, C711S147000, C711S153000, C711S157000

Reexamination Certificate

active

07872657

ABSTRACT:
Systems and methods for addressing memory where data is interleaved across different banks using different interleaving granularities improve graphics memory bandwidth by distributing graphics data for efficient access during rendering. Various partition strides may be selected to modify the number of sequential addresses mapped to each DRAM and change the interleaving granularity. A memory addressing scheme is used to allow different partition strides for each virtual memory page without causing memory aliasing problems in which physical memory locations in one virtual memory page are also mapped to another virtual memory page. When a physical memory address lies within a virtual memory page crossing region, the smallest partition stride is used to access the physical memory.

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