Memory addressing method and apparatus therefor

Details Memory addressing method and apparatus therefor Memory addressing method and apparatus therefor

1994-12-21

1996-02-20

Fears, Terrell W.

Static information storage and retrieval

Addressing

Plural blocks or banks

365203, 36523003, G11C 1300

Patent

active

054935350

ABSTRACT:
A memory addressing method and apparatus therefor having a pair of cell blocks is characterized in that the pair of cell blocks are alternately column-addressed in such a manner that the column line of one cell block is pre-charged while the column line of the other cell block is addressed, and that subsequently, the pre-charged column line of the other cell block is addressed while the next column line of the one cell block is pre-charged. Therefore, the memory device wherein a plurality of cell blocks are alternately addressed can achieve an approximately doubled speed of operation.

REFERENCES:
patent: 5416746 (1995-05-01), Sato et al.

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