Memory address translation in a data processing system

Details Memory address translation in a data processing system Memory address translation in a data processing system

1999-02-19

2002-03-05

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S203000, C711S204000, C711S213000

Reexamination Certificate

active

06353879

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to data processing systems. More particularly, this invention relates to data processing systems in which a virtual address produced by a processor core is translated into a mapped address for use in a memory access.
2. Description of the Prior Art
It is known to provide data processing systems in which a virtual address generated by a processor core for a memory access is translated to a mapped address. The mapped address is then used in the memory access. Such address mappings facilitate the efficient use of the memory resources of the system and the provision of multi-tasking.
A potential limiting factor in the speed of operation of a data processing system is the time taken to issue the mapped address to the memory system. The address translation from the virtual address to the mapped address may often be part of the critical path in determining the maximum processor speed. Accordingly, measures that can alleviate this potential constraint are strongly advantageous.
SUMMARY OF THE INVENTION
Viewed from one aspect the present invention provides apparatus for data processing, said apparatus comprising:
(i) a memory for storing data at mapped addresses within said memory;
(ii) a processor core for requesting a memory access to a virtual address within said memory;
(iii) an address translation circuit for performing a translation of said virtual address to a mapped address in accordance with a current address mapping prediction;
(iv) a memory accessing circuit for accessing data from said memory using said mapped address; and
(v) a mapping validity circuit for determining if said translation is valid for use in said memory access; wherein
(vi) said mapping validity circuit does not determine if said translation is valid until after said memory accessing circuit has commenced said memory access; and further comprising
(vii) an abort circuit for aborting said memory access if said translation is invalid; and
(viii) a restart circuit for restarting said memory access with a valid translation of said virtual address to a valid mapped address.
The address mapping performed is usually controlled by an address mapping parameter. Determining the correct address mapping parameter to use for each translation can introduce an additional delay in the issuing of the mapped address and so adversely impact the critical path time and hence overall processor speed. The present invention recognizes this constraint and reduces its effect by predicting the mapping to be used on each occasion and so generating a mapped address before it has been confirmed that the current address mapping will indeed continue to be used. If the prediction of the address mapping turns out to be incorrect, then the memory access that has already been initiated is aborted. The memory access is then restarted using the correct mapped address.
A possible prediction technique is to assume the current address mapping will remain unchanged, and this will lead to some incorrect translations being performed and memory accesses initiated, with these then having to be aborted. Providing a system which makes such “mistakes” would generally be regarded as disadvantageous. However, removing the need to wait for the determination of the validity of the current address mapping from the critical path in the address translation can allow the overall cycle time of the system to be reduced. In practice it is found that the current address mapping generally remains unchanged for long sequences of memory accesses and the time saved by removing the validity check from the critical path more than compensates for the occasional memory access needing to be aborted due to an incorrect assumption being made regarding the address translation.
It will be appreciated that the mapped address produced by the address translation circuit could have many forms, such as the physical address. However, in preferred embodiments of the invention said mapped address is an intermediate form between said virtual address to said physical address.
Providing such a partially translated mapped address may allow more efficient operation within a hierarchical memory structure, e.g. one level of translation being used to accommodate multi-tasking and a further level of translation to the physical address being used to accommodate the peculiarities of the particular hardware implementation.
In this context it is advantageous to provide embodiments in which said memory accessing circuit includes a memory management unit that translates said mapped address to a physical address.
A memory management unit can be used to perform address translation to reach the physical address.
Whilst it is possible to utilize the invention in a system in which the main memory is directly addressed, in preferred embodiments of the system there is provided cache memory, data within said cache being addressed by said mapped address.
A system having a cache memory is generally able to return cached data to the processor core at high speed and in such systems the advantage of reducing any critical path constraint associated with address translation becomes more significant.
The address translation performed by the address translation circuit could take many forms. However, in preferred embodiments said address translation circuit has a translation mode which replaces a bit field within said virtual address with a bit field specified by said address mapping.
Replacing a bit field within the virtual address with another bit field specified by the address mapping allows powerful control of the memory resources whilst being comparatively easy to control and manage.
The advantages associated with bit field replacement in the translation mode are particularly strong in embodiments in which said bit field specified by said address mapping parameter is one-to-one correspondence to a process identifier that is set under program control.
Having a program controlled process identifier used as the replacement bit field is particularly well suited for multi-tasking environments with multiple processes active at any given time.
In order to provide higher level control of the basic operation of the system preferred embodiments of the invention are such that said address translation circuit has a transparent mode in which said bit field within said virtual address is passed unaltered.
Providing a transparent mode allows the core operating system code, and the like, to directly address memory locations without the potential complication of the intervening address translation circuit.
A particularly efficient way of performing the validity check on the address translation such that the result is available in good time to abort a memory access if necessary is one in which said mapping validity circuit compares for equality said bit field within said virtual address of a current memory access with a predetermined bit field to produce an equality result and if said equality result differs from that of a predicted result swaps between said translation mode and said transparent mode.
The programmers model of the system for concurrently executing processes (threads) can be simplified if each process has its address space mapped to start at zero. In order to accommodate this in preferred embodiments said predetermined bit field is all zeros.
It will be appreciated that the memory access may be aborted in a number of different ways. Particularly suitable ways of aborting a memory access without excessive power consumption and without the need for a large amount of circuitry to recover state are ones in which the processor core clock signal is stretched upon abort or the processor core clock signal continues but with the processor controller in a wait state.
Viewed from another aspect the present invention provides a method of data processing, said method comprising the steps of:
(i) storing data at mapped addresses within a memory;
(ii) requesting a memory access to a virtual address within said memory;
(iii) performing a translation of sai

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