Memory address generator with scheduled write and read...

Details Memory address generator with scheduled write and read... Memory address generator with scheduled write and read...

2006-06-20

2006-06-20

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Read/write circuit

C365S189070, C365S236000

Reexamination Certificate

active

07064987

ABSTRACT:
A memory address generator includes a write address generator for generating write addresses to be used in writing of data units of an input data block into a memory device in a non-raster scan arrangement, a read address generator for generating read addresses to be used in reading of the data units of the input data block from the memory device in a raster scan arrangement, and a scan pattern analyzer for enabling the read address generator after enabling the write address generator such that an optimum number of the write addresses for the writing of the input data block has been generated prior to generation of the read addresses for the reading of the input data block in order to ensure that the reading of each of the data units from the memory device can lag the writing of each of the data units into the memory device.

REFERENCES:
patent: 5745724 (1998-04-01), Favor et al.
patent: 6853385 (2005-02-01), MacInnis et al.
patent: 2005/0122335 (2005-06-01), Maclnnis et al.

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