Memory address generator circuit and semiconductor memory device

Details Memory address generator circuit and semiconductor memory device Memory address generator circuit and semiconductor memory device

1999-03-16

2000-08-15

Mai, Son

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365236, 326105, G11C 800

Patent

active

061046647

ABSTRACT:
A semiconductor storage device (1100) having a burst mode capability for accomplishing a rapid read/write operation is disclosed. Included is a memory address generator circuit (100) having an address counter (102) which latches and increments the n least significant bits of a start address containing m bits, the address counter (102) producing a count value. An address latch (104) latches the m-n most significant bits of the start address, and an end address arithmetic circuit (106) produces a burst end address by subtracting 1 from the start address n least significant bits. A comparator circuit (108) generates a burst end signal (BSTEND) based on the comparison of the count value and the burst end address, the comparison being done by way of a generation of coincidence signals (k0-k2) by coincidence detector circuits included in the comparator circuit (108). Read/write addresses are produced for the semiconductor storage device where the m-n bits in the address latch (104) form the more significant bits of the read/write address and the count value form the less significant bits of the read/write address. The read/write operation for the memory is completed by stopping the increment operation of the address counter (102) when the burst end signal is generated.

REFERENCES:
patent: 5650968 (1997-07-01), Dosaka et al.
patent: 5652723 (1997-07-01), Dosaka et al.
patent: 5703828 (1997-12-01), Park et al.
patent: 5805928 (1998-09-01), Lee
patent: 5978303 (1999-11-01), Takasugi et al.

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