Memory activation devices and methods

Details Memory activation devices and methods Memory activation devices and methods

1998-08-11

2000-03-21

Phan, Trong

Static information storage and retrieval

Read/write circuit

Signals

36523006, G11C 700, G11C 800

Patent

active

060409983

ABSTRACT:
An apparatus and method are disclosed for activating a memory location within a memory device. In an apparatus aspect of the invention, a memory device is disclosed. The memory device includes an enable unit arranged to receive a plurality of address signals and a clock signal and to output an activation signal. The address signals has an associated worst case delay, and the enable unit is further arranged to generate an enable signal that is delayed from the clock signal by at least about the worst case delay. The memory device further includes a memory array arranged to receive the activation signal in response to which a corresponding memory location is activated.

REFERENCES:
patent: 4425633 (1984-01-01), Swain
patent: 5500818 (1996-03-01), Chang et al.
patent: 5530677 (1996-06-01), Grover et al.
patent: 5652732 (1997-07-01), Shah
patent: 5835421 (1998-11-01), Pham et al.
patent: 5844857 (1998-12-01), Son et al.

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