Memory access system and method using de-coupled read and...

Details Memory access system and method using de-coupled read and... Memory access system and method using de-coupled read and...

2004-09-30

2008-12-16

Peikari, B. James (Department: 2189)

Static information storage and retrieval

Read/write circuit

Separate read and write bus

C365S233110, C365S189040, C365S220000, C710S125000, C711S001000, C711S169000, C711S168000, C711S167000

Reexamination Certificate

active

07466607

ABSTRACT:
A de-coupled memory access system including a memory access control circuit is configured to generate first and second independent, de-coupled time references. The memory access control circuit includes a read initiate circuit responsive to the first time reference and a read signal for generating a read enable signal, and a write initiate circuit responsive to the second time reference and a write signal for generating a write enable signal independent of the read enable signal for providing independent, de-coupled write access to a memory array.

REFERENCES:
patent: 5717653 (1998-02-01), Suzuki
patent: 5845314 (1998-12-01), Ishida
patent: 6075730 (2000-06-01), Barth et al.
patent: 6959016 (2005-10-01), Keeth et al.
patent: 7006404 (2006-02-01), Manapat et al.
patent: 2003/0172241 (2003-09-01), Shirota

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