Memory access prediction in a data processing apparatus

Details Memory access prediction in a data processing apparatus Memory access prediction in a data processing apparatus

2005-02-01

2005-02-01

Bataille, Pierre (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S213000, C711S218000, C711S214000, C711S137000, C712S230000, C712S239000, C712S245000

Reexamination Certificate

active

06851033

ABSTRACT:
The present invention relates to techniques for predicting memory access in a data processing apparatus and particular to a technique for determining whether a data item to be accessed crosses an address boundary and will hence require multiple memory accesses. An earlier indication can be provided that at least two memory accesses may be required to access a data item by performing a prediction based upon one or more operands generated from a memory instruction instead of waiting for a memory access generation stage to generate the memory access. Prediction logic can generate a prediction signal to prevent the memory access generation stage from receiving signals from a preceding pipeline stage while at least two memory accesses are being generated.

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patent: 6629234 (2003-09-01), Col
patent: 20020026545 (2002-02-01), Yoshida et al.
patent: 02000305779 (2000-11-01), None

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