Computer graphics processing and selective visual display system – Computer graphics display memory system – Graphic display memory controller
Reexamination Certificate
2002-04-22
2004-06-22
Tung, Kee M. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Graphic display memory controller
Reexamination Certificate
active
06753871
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a memory access method and, more particularly, to a memory access method of a video decoding system that utilizes a method of overlapping boundary data to reduce cross-page penalties when reading data.
2. Description of the Related Art
In many modern video decoding systems, such as MPEG-I, MPEG-II, and H261, inter-frame compression is used to reduce the redundancies between pictures and results in substantial data reduction. These systems all involve algorithms based on a common core of compression techniques, i.e. predictive and/or interpolative inter-frame encoding. The motion compensation is block-based and each prediction block has associated with motion vectors. The motion compensation operation involves reading the prediction blocks from reference pictures according to the motion vector information. Generally speaking, the reference pictures are quite large and typically stored in DRAM. The DRAM consists of several memory banks, and each bank in turns consists of many memory pages. Some additional overhead cycles, such as pre-charging and activating a memory page, are needed before accessing data in a memory page. Hence, when the current accessed page is different from the previous one, some overhead cycles, i.e. cross-page penalties, will occur. The cross-page penalties will significantly lower the bandwidth of reading prediction blocks from DRAM.
In order to reduce cross-page penalties, the prediction blocks should occupy as few pages as possible, and they should be read out page-by-page.
FIG. 1
is a schematic diagram showing reference picture data stored in blocks. As shown in
FIG. 1
, the size of the reference picture is 720×576 pixels, and the size of each macro-block is 16×16 pixels. If the DRAM's page size is 1024 bytes, then each page may store four macro-blocks. The storing method in
FIG. 1
is that each page (shown by thick lines) stores four vertical macro-blocks (shown by thin lines). When reading the dash-lined prediction block A, the data areas A
1
, A
2
, A
3
, and A
4
of prediction block A are allocated in four different pages; therefore, it is necessary to have three cross-page penalties.
Although cross page penalties can be substantially reduced by page-by-page read sequence, it still becomes an inevitable and inherent DRAM bandwidth bottleneck in very high bandwidth applications such as HDTV video decoding. Especially, such high bandwidth application usually has real time decoding requirement. Hence, the burst and large memory read action during motion compensation process may fail to achieve real-time decoding due to excessive page crossings.
SUMMARY OF THE INVENTION
In view of the above-mentioned problems, the object of the invention is to provide a memory access method, in which a virtual page is formed through overlapping boundary data at page boundaries to logically enlarge DRAM page size so as to reduce or entirely prevent cross-page penalties.
In order to achieve the above-mentioned object, the memory access method of the invention is to overlap partial boundary data at page boundary in order to reduce or eliminate cross-page penalties when reading data. The method includes the following steps: the first is a determining step, to determine the maximum size of prediction blocks; the second is a storing step, to overlap partial boundary data at adjacent pages; and the final is a reading step, to read prediction block from the page having all the data of the prediction block when the prediction block is at the boundary with overlapping data.
Hence, the invention utilizes a method of overlapping boundary data to eliminate or reduce cross-page penalties when reading the block data so as to increase the memory bandwidth as well as the reading speed.
REFERENCES:
patent: 5675387 (1997-10-01), Hoogenboom et al.
patent: 6005624 (1999-12-01), Vainsencher
Birch & Stewart Kolasch & Birch, LLP
Mediatek Inc.
Tung Kee M.
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