Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate
2011-07-12
2011-07-12
Portka, Gary J (Department: 2187)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
C345S547000, C711S157000
Reexamination Certificate
active
07979622
ABSTRACT:
A memory access method intended for a memory required to provide an interval of a predetermined number of clock cycles or longer between successive occurrences of access when the same bank is successively accessed, and that eliminates an idle time between successive occurrences of access to allow for improved performance. Pieces of data are written into 0th, the first, the second, and the third banks, respectively. No idle time is caused between successive occurrences of access because different banks are successively accessed. Since a burst length of each of the pieces of data is eight, an interval of 16 cycles which is longer than 15 cycles is provided between a start of writing of first data and a start of second writing of data. Accordingly, no idle time is caused also between completion of writing of the first data and start of writing of the second data.
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Megachips Corporation
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
Portka Gary J
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