Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2002-04-03
2003-05-27
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S156000, C711S205000, C711S221000, C711S005000
Reexamination Certificate
active
06571323
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computer memory management, and more particularly, to a memory-access management method and system which is designed for use with an SDRAM (Synchronous Dynamic Random-Access Memory) or the like, for the purpose of increasing the performance of memory access to the SDRAM by means of tracking the memory-access history of previous access operations.
2. Description of Related Art
In a computer system, a master unit is used to control the access operations, whether read or write, to the primary memory of the computer system. In general, the memory access would be focused on some particular segments rather than all the segments in the primary memory; in other words, some segments would be most often accessed than others. In the design of a memory-access management system, the primary concern is directed to the reduction of overhead and latency.
The SDRAM (Synchronous Dynamic Random-Access Memory) is a new type of memory device. Each SDRAM unit is typically partitioned into four sub-banks, each sub-bank containing a number of pages and only one of which can be opened at the same time. In other words, in each SDRAM unit, at most four pages can be opened at the same time. Conventionally, each sub-bank is associated with one memory control unit for managing the pages in the sub-bank. Therefore, for each SDRAM unit, four memory control units are required. This page management scheme, however, has the following drawbacks.
In the case a memory slot is unused or is mounted with an SDRAM unit that contains only two sub-banks, the provision of four memory control units will not be fully utilized, and therefore is cost-ineffective in utilization.
When VC-SDRAM (Virtual Channel SDRAM) is used, since each VC-SDRAM unit can provide 16 channels, the provision of four memory control units will allow only four of the 16 channels to be usable and the other 12 channels to be unused. A solution to this problem is to provide 16 memory control units for each VC-SDRAM unit. However, this solution would require a very large circuit layout area to incorporate all the 16 memory control units, and therefore is quite cost-ineffective. Moreover, the use of 16 memory control units would cause a large delay to the access operation and therefore is unsuitable for use with a high-speed computer system.
In addition, conventionally, it provides registers to store the addresses of the memory pages, in which the number of the registers is equal to or great than the number of the memory pages. For example, assuming there are 4 DIMM module, each DIMM has two bank and each bank has 4 sub-bank. Because one memory page corresponds to a sub-bank, and therefore it requires 32 registers to store 32 addresses data of the memory pages. Accordingly, the layout area for the registers is large.
There exists, therefore, a need for a new memory-access management method and system which can be used with various types of memory devices, including SDRAM, VC-SDRAM, and EDO DRAM.
SUMMARY OF THE INVENTION
It is therefore an objective of this invention to provide a new computer memory-access management method and system, which is designed for use with a DRAM or the like, for the purpose of increasing the performance of memory access to the DRAM.
In accordance with the foregoing and other objectives of this invention, a new computer memory-access management method and system is provided.
According to one embodiment of the present invention, the present invention provides a memory-page management system for tracking an access history of a memory unit having N memory pages. The memory-page management system has a managing device for managing the N memory pages. According to the embodiment, the managing device further comprises a page register unit. The page register unit is used for storing K storage units, each of which stores an address data corresponding to one of the memory pages. The utilization-rate register unit is coupled to the page register circuit, and used for monitoring utilizations of the storage units. In the practical design of the present invention, the number K is less than the number N.
Additionally, the managing device can further comprise a comparison unit coupled to the page register unit, which is used for receiving an access address and outputting a hit signal according to a compared result of the access address and the address data stored in the page register unit. In operation, the hit signal is activated when the access address hits one of the address data stored in the page register unit. The managing device can further comprise a validity-checking unit, which is coupled to the page register unit for determining whether the address data stored in the page register unit are valid.
According to another embodiment, the invention further provides a memory-page management system for tracking an access history of a memory unit, which comprises a memory unit and a managing device. The memory unit is configured to have N memory pages. The managing device is used for managing the N memory pages, further comprising a page register unit. The page register unit is used for storing K storage units, each of which stores an address data of the memory page. The utilization-rate register unit is coupled to the page register circuit, and used for monitoring utilizations of the storage units. In practical design, the number K is less than the number N.
Additionally, the managing device can further comprise a comparison unit coupled to the page register unit, which is used for receiving an access address and outputting a hit signal according to a compared result of the access address and the address data stored in the page register unit. In operation, the hit signal is activated when the access address hits one of the address data stored in the page register unit. The managing device can further comprise a validity-checking unit, which is coupled to the page register unit for determining whether the address data stored in the page register unit are valid.
The memory-access management method and system of the invention has the following advantages. First, it can increase the memory access performance by tracking the history of the previous access operations to the SDRAM. Second, it can judge in advance whether the next pipelined access requires precharge or not; if yes, a precharge-enable signal is issued at the time the current access is being handled. As a result, the delay in access can be reduced. Overall, the memory access performance is increased. Conventionally, a memory-page management system for tracking an access history of a memory unit comprises a memory having a plurality of memory pages; and a page register unit having a plurality of storage units for storing the address data of the memory pages. Each storage unit stores an address data of one memory page and the number of the storage units of the page register unit is equal to the number of the memory pages. For example, assuming that the system includes 4 DIMMs, each DIMM has 2 banks and each bank has 4 sub-banks, so that each sub-bank corresponds to one memory page. Therefore, the system memory has 32 memory pages totally. Namely, according to the conventional technology, 32 storage units, such as 32 registers are required. In contrast, according to the invention, the number of the registers used in the invention can be, for example, reduced to as half as the number of the registers used in the conventional technology. Namely, 16 registers are only required, and therefore, the area for 16 registers can be saved in the chip layout.
REFERENCES:
patent: 5584014 (1996-12-01), Nayfeh et al.
patent: 5781922 (1998-07-01), Braceras et al.
patent: 6069638 (2000-05-01), Porterfield
patent: 6286075 (2001-09-01), Stracovsky et al.
Kao Chih-kuo
Lai Jiin
Anderson Matthew D.
J.C. Patents
Kim Matthew
Via Technologies Inc.
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