Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses
Reexamination Certificate
2003-11-19
2008-11-25
Kim, Matt (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Generating a particular pattern/sequence of addresses
C712S029000
Reexamination Certificate
active
07457936
ABSTRACT:
A compilation method includes converting memory access instructions that read or write less than a minimum data access unit (MDAU) to memory access instructions that read or write a multiple of the minimum data access unit, converting the memory access instructions into a format including a base address plus an offset, grouping subsets of the converted memory access instructions into partitions, and vectorizing the converted memory access instructions in the subsets that match instruction patterns.
REFERENCES:
patent: 5850551 (1998-12-01), Takayama et al.
patent: 6099585 (2000-08-01), Godfrey
patent: 6286134 (2001-09-01), Click, Jr. et al.
patent: 6292938 (2001-09-01), Sarkar et al.
patent: 6334171 (2001-12-01), Hill et al.
patent: 6356270 (2002-03-01), Pentkovski et al.
patent: 6434639 (2002-08-01), Haghighi
patent: 6496905 (2002-12-01), Yoshioka et al.
patent: 6571319 (2003-05-01), Tremblay et al.
patent: 6681311 (2004-01-01), Gaskins et al.
patent: 7085887 (2006-08-01), Gaither
patent: 2002/0169921 (2002-11-01), Saitoh
patent: 2002/0184460 (2002-12-01), Tremblay et al.
patent: 2003/0061531 (2003-03-01), Fletcher et al.
patent: 2003/0217223 (2003-11-01), Nino et al.
patent: 2004/0006667 (2004-01-01), Bik et al.
patent: 2004/0088503 (2004-05-01), Miyachi et al.
patent: 2004/0158677 (2004-08-01), Dodd
patent: 2005/0044326 (2005-02-01), Gaither
patent: 2005/0097301 (2005-05-01), Ben-David et al.
patent: 0 609 903 (1994-08-01), None
patent: 0 742 518 (1996-11-01), None
patent: WO 00/22513 (2000-04-01), None
Microsoft Press Dictionary, 1997, Microsoft Press, 3rded., pp. 166, 170, 332.421.
Microsoft Computer Dictionary, 2002, Microsoft Press, Fifth Edition, pp. 182, 186, 216, 371, 466.
International Search Report, dated Feb. 5, 2004 issued by the ISA/CN in corresponding International Application Serial No. PCT/CN03/00989.
Bik et al., “Automatic Intra-Register Vectorization for the Intel Architecture”, International Journal of Parallel Programming 30(2):65-98, Apr. 2002.
Dai Jinquan (Jason)
Harrison Luddy (Williams)
Huang Bo
Li Long (Paul)
Dare Ryan
Fish & Richardson P.C.
Intel Corporation
Kim Matt
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