Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2000-05-02
2004-07-27
Elmore, Reba I. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S169000
Reexamination Certificate
active
06769049
ABSTRACT:
The invention relates to apparatus and methods for accessing a computer memory.
BACKGROUND OF THE INVENTION
Computer systems may comprise a plurality of parallel execution pipelines used to generate access addresses for load and store operations in the memory, as well as data for storing in the memory. For instructions which enter the pipelines in the same cycle, there may be different times required in the execution pipelines before results are available for use in memory accesses. Some parallel instructions may require more cycles in the relevant execution pipeline and this is particularly so in the case of pipelines used for arithmetic calculations. To allow access decoupling between pipelines generating addresses and those generating data values, it may be desirable to store addresses and data values in a memory access unit.
It is an object of the present invention to provide improved apparatus and methods for controlling access to a computer memory.
SUMMARY OF THE INVENTION
The invention provides a computer system having a memory, a plurality of parallel execution pipelines, and a memory access controller. At least one first parallel execution pipeline forms part of a data unit operable to provide data for storing in the memory, and at least one second parallel execution pipeline forms part of an address unit operable to address the memory for load or store accesses to the memory. The memory access controller includes circuitry for forming a store address queue which has addresses for store operations in the memory, load address storage which has addresses for load operations in the memory, and a data queue for data awaiting a store operation in the memory. The memory access controller has selector circuitry responsive to both the store address queue and to load addresses received by the controller and operable to select either a store or a load operation. The selector circuitry is arranged to compare addresses on the store address queue with a received load address and to select a load operation before a store operation if no address match is found in the comparison, and to select a store operation before a load operation if an address match is found. Preferably the received load address is put on a load address queue if a store operation is selected first.
Preferably the memory access controller includes a guard value queue holding guard values corresponding to store accesses in the store address queues, the guard values indicating if respective memory accesses are to be effected or not. The controller includes control circuitry to determine a guard value for the queue for each operation in the store address queues and to control whether the access is effected in accordance with the guard value.
Preferably an interface is provided between the memory access controller and the data and address units, the interface including at least one load data queue for data which has been received from load access operations in the memory.
Preferably the memory forms a plurality of separately addressable regions including X and Y memory regions, with separate queues being provided in the data memory controller for data awaiting store operations in the X and Y memory regions. Preferably separate queues are provided in the data memory controller for store addresses and load addresses for use in the X and Y memory regions. Preferably the memory access controller includes at least one data routing queue for selectively adding data to the X or Y store data queue. Preferably the memory access controller includes at least one guard routing queue for selectively adding guard values to an X or Y guard value queue.
Preferably the plurality of parallel execution pipelines include at least two pipelines in the data unit for executing arithmetic operations and at least two pipelines in the address unit for executing memory addressing operations. Preferably transfer circuitry is provided to add data from any pipeline in the data unit to either the X or Y store data queues and to add load or store addresses from any pipeline in the address unit to either the X or Y address queues in the memory access controller. Preferably the memory access controller includes at least one store data queue for data from the data unit and at least one store data :queue for data from the address unit. Preferably clock circuitry is provided to maintain the required order of execution of a plurality of instructions which enter the parallel pipelines in the same cycle.
The invention also includes a method of operating a computer system by executing instructions in a plurality of execution pipelines. At least one of the pipelines provides data for storing in a memory and at least one of the pipelines forms an address for a load or store access to the memory. The method includes forming a store address queue which has addresses for store operations in the memory, forming a load address storage which has addresses for load operations in the memory, and forming a data queue for data awaiting a store operation in the memory, and selecting either a store or a load operation by comparing addresses on the store address queue with a received load address to determine if any address match is found. In response to an address match, the method includes selecting a store operation before a load operation, and in the absence of an address match includes selecting a load operation before a store operation.
Preferably the method includes forming a queue of guard values corresponding to store accesses in the store address queues, determining for each store address the guard value for the respective operation in the store address queues and determining whether memory access is effected in accordance with the guard value.
REFERENCES:
patent: 5742831 (1998-04-01), Creta
patent: 5754812 (1998-05-01), Favor et al.
patent: 5918033 (1999-06-01), Heeb et al.
patent: 6094711 (2000-07-01), Wong
patent: 6119204 (2000-09-01), Chang et al.
patent: 6240509 (2001-05-01), Akkary
patent: 6317810 (2001-11-01), Lopez-Aguado et al.
patent: 0 871 109 (1998-10-01), None
Gathering Store Instructions in a Superscalar Processor, IBM Technical Disclosure Bulletin, vol. 39, No. 9, Sep. 1996, pp. 103-106, XP000638245.
Bernard Bruno
Dabbagh Ahmed
Grossier Nicolas
Elmore Reba I.
Jorgenson Lisa K.
Morris James H.
STMicroelectronics S.A.
Wolf Greenfield & Sacks P.C.
LandOfFree
Memory access in a computer system having parallel execution... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory access in a computer system having parallel execution..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory access in a computer system having parallel execution... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3231659