Memory access engine having multi-level command structure

Details Memory access engine having multi-level command structure Memory access engine having multi-level command structure

2007-11-27

2007-11-27

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S023000, C710S024000, C710S028000, C710S052000, C710S053000, C710S054000, C710S055000, C710S056000, C710S057000

Reexamination Certificate

active

10404074

ABSTRACT:
A direct memory access system utilizing a local memory that stores a plurality of DMA command lists, each comprising at least one DMA command. A command queue can hold a plurality of entries, each entry comprising a pointer field and a sequence field. The pointer field points to one of the DMA command lists. The sequence field holds a sequence value. A DMA engine accesses an entry in the command queue and then accesses the DMA commands of the DMA command list pointed to by the pointer field of the accessed entry. The DMA engine performs the DMA operations specified by the accessed DMA commands. The DMA engine makes available the sequence value held in the sequence field of the accessed entry when all of the DMA commands in the accessed command list have been performed. In one embodiment, the command queue is part of the DMA engine.

REFERENCES:
patent: 4783730 (1988-11-01), Fischer
patent: 4807111 (1989-02-01), Cohen et al.
patent: 5237661 (1993-08-01), Kawamura et al.
patent: 5404522 (1995-04-01), Carmon et al.
patent: 5555396 (1996-09-01), Alferness et al.
patent: 5577211 (1996-11-01), Annapareddy et al.
patent: 5600646 (1997-02-01), Polomski
patent: 5634099 (1997-05-01), Andrews et al.
patent: 5708849 (1998-01-01), Coke et al.
patent: 5797041 (1998-08-01), Yasue et al.
patent: 5809334 (1998-09-01), Galdun et al.
patent: 5923852 (1999-07-01), Lee et al.
patent: 5933654 (1999-08-01), Galdun et al.
patent: 5968153 (1999-10-01), Wheeler et al.
patent: 5970069 (1999-10-01), Kumar et al.
patent: 6052387 (2000-04-01), Chow et al.
patent: 6070194 (2000-05-01), Yu et al.
patent: 6145016 (2000-11-01), Lai et al.
patent: 6167465 (2000-12-01), Parvin et al.
patent: 6205494 (2001-03-01), Williams
patent: 6212593 (2001-04-01), Pham et al.
patent: 6314477 (2001-11-01), Cowger et al.
patent: 6538656 (2003-03-01), Cheung et al.
patent: 6714553 (2004-03-01), Poole et al.
patent: 6721320 (2004-04-01), Hoglund et al.
patent: 6738358 (2004-05-01), Bist et al.
patent: 2001/0021949 (2001-09-01), Blightman et al.
patent: 2001/0049755 (2001-12-01), Kagan et al.
U.S. Appl. No. 09/437,208 entitled “Graphics Display System”, filed Nov. 9, 1999, Inventor: Alexander G. MacInnis et al.
U.S. Appl. No. 09/641,374 entitled “Video Audio And Graphics Decode, Composite And Display System”, filed Aug. 18, 2000, Inventor: Alexander G. MacInnis et al.
U.S. Appl. No. 09/641,936 entitled “Video And Graphics System With An MPEG Video Decoder For Concurrent Multi-Row Decoding”, filed Aug. 18, 2000, Inventor: Ramanujan K. Valmiki et al.
U.S. Appl. No. 09/643,223 entitled “Video And Graphics System With MPEG Specific Data Transfer Commands”, filed Aug. 18, 2000, Inventor: Ramanujan K. Valmiki et al.
U.S. Appl. No. 09/640,870 entitled “Video And Graphics System With Video Scaling”, filed Aug. 18, 2000, Inventor: Alexander G. MacInnis et al.
U.S. Appl. No. 09/641,930 entitled “Video And Graphics System With A Video Transport Processor”, filed Aug. 18, 2000, Inventor: Ramanujan K. Valmiki et al.
U.S. Appl. No. 09/641,935 entitled “Video And Graphics System With Parallel Processing Of Graphics Windows”, filed Aug. 18, 2000, Inventor: Alexander G. MacInnis et al.
U.S. Appl. No. 09/642,510 entitled “Video And Graphics System With A Single-Port RAM”, filed Aug. 18, 2000, Inventor: Xiaodong Xie.
U.S. Appl. No. 09/642,458 entitled “Video And Graphics System With An Integrated System Bridge Controller”, Inventor: Alexander G. MacInnis et al.
Hatabu et al, “QVGA/CIF Resolution MPEG-4 Video Codec Based on a Low-Power and General-Purpose DSP”, Signal Processing System, 2002, SIPS '02, IEEE Workshop on Oct. 16, 2002, XP010618570.

Affiliated with

Also associated with

Rating

Memory access engine having multi-level command structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory access engine having multi-level command structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory access engine having multi-level command structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3880131