Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2001-10-24
2004-09-07
Elmore, Reba I. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S154000, C711S163000, C711S168000, C711S170000
Reexamination Certificate
active
06789174
ABSTRACT:
FIELD OF THE INVENTION
A single chip microcomputer or an MCU (Micro Controller Unit) comprises a CPU as a first function device and an RTD (Real Time Debugger) or a DMA (Direct Memory Access) as a second function device, both of which can access a memory (RAM). The present invention relates to a memory access device in which both the first and second function devices can access the memory at the same time.
BACKGROUND OF THE INVENTION
In a single chip microcomputer or an MCU used for control of various types of industrial equipment and consumer products, including control of an automobile engine, an RTD, other than a CPU, a memory (RAM), and various kinds of peripheral devices have been built in and read/write of the built-in memory has been configured to be performed through a serial input/output interface of a clock synchronization type, without stopping the CPU. The RTD can perform RAM access in the case of no RAM access from the CPU, as the above RTD is connected to the RAM using a dedicated bus.
In such a single chip microcomputer with a built-in RTD, the CPU has been usually configured to have top priority for acquisition of a right of access in the case of simultaneous accesses to the memory (RAM) from the CPU and the RTD, and a so-called cycle stealing method, which access from the RTD may be realized just after completion of the access from the CPU, has been used. That is, a request signal for access to the RAM from the RTD has been conventionally generated just after completion of access from the CPU, as shown by the bottom two lines in
FIG. 11
, when there are simultaneous accesses to the RAM from the CPU and the RTD, as shown by top two lines in FIG.
11
.
Therefore, the access to the RAM from the RTD has been conventionally delayed for a long time, when access from the CPU to the RAM is frequently and continuously generated. That is, when access from the CPU to the RAM is continuously generated for a long time, as shown in
FIG. 12
, the access from the RTD has been executed after completion of the access from the CPU, even if the access from the RTD to the RAM is generated during the access from the CPU.
Such a phenomenon is similarly generated too whan the DMA is built in as a device accessible to the memory.
In the Japanese Patent Application Laid-Open No. 10-312355 discloses a system in which both a CPU and a DMA are accessible to a RAM, and an RMA storage area is divided into two memory blocks consisting of an upper half word block and lower half word block; the CPU alternately accesses these two memory blocks at a predetermined cycle; and the DMA alternately has, at the same cycle as that of the CPU, an access to a memory block, to which the CPU is not having an access, among the two blocks. That is, the above conventional technology has required two cycles, when the CPU or the DMA accesses one word consisting of an upper half and a lower half of the word.
There is a problem in the above conventional technology that access to one word requires two access cycles, as the simultaneous accesses to the RAM from both the CPU and the DMA may be realized by division of a data area (word) in the RAM storage area into two pieces, an upper half and a lower half of the word, and by a manner in which the CPU and the DMA accesses respectively a word area (upper half word area, or lower half word area) which the other side is not accessing. There is also another problem that the circuit structure becomes complex and the scale of the structure becomes large, since access for one word requires two access cycles in the structure, and a first multiplexer for switching selection between the CPU address bus and the DMA address bus is required at the input side of the RAM, and a second multiplexer for synthesizing the upper half word data and the lower half word data is provided at the output side of the RAM.
SUMMARY OF THE INVENTION
It is an object of this invention to obtain a memory access device in which simultaneous accesses to a memory from a CPU and other function devices may be realized by a simple circuit structure and at the same time access to data of one word in the memory may be realized at one time access in a single chip microcomputer comprising a function device, other than the CPU, such as an RTD or a DMA accessible to the memory.
The memory access device according to the present invention comprises a CPU as a first function device and a desired second function device. Address buses and data buses of the first and second function devices are connected to a memory. Moreover, a memory address space in the memory is divided into a plurality of blocks so that each block has continuous address areas. There is further provided a memory access control unit which checks whether memory blocks accessed by the first and second function devices are same. The memory access control unit permits simultaneous access by the first and second function devices to the memory blocks when the memory block accessed by the first and second function devices are not same.
According to the present invention, the memory address space is divided into a plurality of blocks so that each block has a continuous address area, and address buses and data buses of the CPU and the second function device (RTD, DMA, and so on) are connected to each of the above divided blocks. And, in the memory access control circuit, simultaneous accesses to the memory from the first and second function devices is configured to be permitted when the memory block accessed by the CPU and the memory block accessed by the second function device are judged and the above blocks are different each other.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.
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patent: 4851991 (1989-07-01), Rubinfeld et al.
patent: 5483640 (1996-01-01), Isfeld et al.
patent: 5615331 (1997-03-01), Toorians et al.
patent: 6185731 (2001-02-01), Maeda et al.
patent: 6256256 (2001-07-01), Rao
patent: 6321331 (2001-11-01), Roy et al.
patent: 10-312355 (1998-11-01), None
Konishi Masayuki
Shimomura Takehiko
Elmore Reba I.
Leydig , Voit & Mayer, Ltd.
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