Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-12-22
2004-06-22
Beausoliel, Robert (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S045000, C714S702000, C717S124000, C717S127000, C717S128000
Reexamination Certificate
active
06754856
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention may be applied to highly embedded high performance digital processors and debug facilities may be provided on chip. Such digital processors may operate with pipelined execution of instruction sequences together with guard or prediction values such that execution of the instruction depends on resolution of the guard value. It is understood that “prediction” and “guard” have the same meaning and the term “guard” will be used hereafter. In the case of long execution pipelines using guarded instructions the guard value may not be resolved until the instruction is well into the pipeline and has been followed by one or more successive instructions entering the pipeline. For some errors it may be possible to effect synchronisation to identify the exact program count associated with the instruction for which the error arises and thereby set a precise program count watch. In some cases, such as for example the memory access operation, it may not be possible to obtain the program count associated with an error without first identifying the memory access address associated with the error. It will be appreciated that unless the program count of the instruction associated with the error has been identified the debug routine may not be operated prior to execution of the instruction associated with the error.
It is an object of the present invention to provide an improved computer system and method of operating a computer system which permits determination of the program count of an instruction for which an error arises in a data memory access operation.
When an error arises in a memory access operation it may not be possible at the time the error is detected to identify the program count of the instruction which gave rise to the memory access error. In accordance with some embodiments of the invention the memory access address giving rise to the error may be used in a data watch operation to identify the program count of the instruction giving rise to the memory access error and the program count may be used in a precise program count watch.
SUMMARY OF THE INVENTION
The invention provides a computer system for executing a sequence of instructions in at least one pipelined execution unit, said system including instruction fetch circuitry for obtaining instructions from a program memory in accordance with a program count, instruction dispatch circuitry for dispatching fetched instructions to said pipelined execution unit, data memory for use in load and store operations, data memory access circuitry for effecting data memory access operations in response to execution of instructions in said pipelined execution unit, and emulator circuitry for use in debug operations, said emulator circuitry including error indicating circuitry to indicate an error in a data memory access operation, snoop circuitry for snooping memory access operation in said data memory access circuitry, synchronising means for synchronising snooped data memory access addresses with respective program counts for the instructions associated with said access addresses, memory mapped storage circuitry responsive to a data memory access error to indicate the data memory address associated with the error, whereby the emulator circuitry may use the data memory address in a subsequent operation to obtain from the synchronising means the specific program count associated with the memory access operation in which the error occurred.
Preferably the emulator circuitry includes diagnostic circuitry to break the instruction sequence dispatched by the dispatch circuitry in response to detection of an error in a data memory access operation.
Preferably the diagnostic circuitry is operable to generate a precise watch of the program count for use in debugging the data memory access operation by instruction break circuitry to break the instruction sequence dispatched by the dispatch circuitry immediately prior to the instruction identified by said specific program count.
Preferably a trap control circuit is connected to receive an input from said data memory access circuitry and respond to detection of a data memory access error, said trap control circuitry being operable to select whether the instruction sequence dispatched by the dispatch circuitry is interrupted or not.
Preferably the trap control circuitry may select an output signal to generate an imprecise trap for use in debugging the data memory access operation by activating the instruction break circuitry to break the instruction sequence dispatched by the dispatch circuitry when the memory access error is detected.
Preferably the synchronising circuitry comprises a plurality of multivalue buffers, each arranged to hold successive values of respective parameters in an order sequence, one of said parameters being successive program counts and another of said parameters being memory access addresses.
Preferably each of said instructions includes a guard value and one of said buffers is arranged to hold commit indicators after resolution of the guard values of instructions fed to the execution pipeline to indicate whether execution of the instruction is committed.
Preferably a plurality of parallel execution pipelines is provided.
The invention includes a method of executing a sequence of instructions in at least one pipelined execution unit of a computer system, which method comprises fetching instructions from a program memory in accordance with a program count, dispatching fetched instructions to said pipelined execution unit, effecting load and store operations in a data memory through data memory access circuitry, and effecting a debug operation to indicate an error in a data memory access operation by snooping memory access operations in said data memory access circuitry, synchronising snooped data memory access addresses with respective program counts for the instructions associated with said access addresses, indicating in memory mapped storage circuitry a data memory address associated with a data memory access error, whereby the data memory address in said memory map storage circuitry may be used in a subsequent operation to obtain a specific program count associated with the memory access operation in which the error occurred.
Preferably the debug operation is effected by a emulator circuitry having diagnostic circuitry which breaks the instruction sequence dispatched by the dispatch circuitry in response to detection of an error in a data memory access operation.
Preferably, after indicating in memory storage circuitry a data memory address associated with a data memory access error, the debug operation includes executing the instruction sequence and snooping the memory access address indicated by the memory map storage circuitry thereby providing the program count of the instruction associated with the data memory access error.
Preferably the diagnostic circuitry operates to generate a precise watch of the program count for use in debugging the data memory access operation by breaking the instruction sequence dispatched by the dispatch circuitry immediately prior to the instruction identified by the specific program count.
Preferably trap control circuitry receives an input from the data memory access circuitry and is responsive to detection of a data memory access error and selects whether the instruction sequence dispatched by the dispatch circuitry is interrupted or not on detection of the data memory access error.
Preferably the trap control circuitry provides an output signal to generate an imprecise trap for use in debugging the data memory access operation by activating the instruction break circuitry to break the instruction sequence dispatched by the dispatch circuitry when the memory access error is detected.
Preferably the data memory access operations are synchronised with respective program counts by loading into multivalue buffers successive values of respective parameters in an ordered sequence, one of the parameters being successive program counts and another of said parameters being memory access addresses.
Prefera
Bernard Bruno
Cofler Andrew
Sename Isabelle
Beausoliel Robert
Jorgenson Lisa K.
McClellan William R.
Puente Emerson
STMicroelectronics S.A.
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