Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1999-01-14
2001-09-25
Ellis, Kevin L. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
Reexamination Certificate
active
06295588
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the implementation of memory access interfaces suitable for multimedia processors.
2. Description of the Related Art
Many computer and multimedia systems require memory access interfaces permitting the transfer of data to and from memory, as well as additional control functions that may be required. This memory may be used to store temporary variables, control information, frame memories for picture storage, and other requirements of the system. Control functions for such memories may include initialization, refresh and memory bank overlapping, also known as ping-ponging. Speed of data transfer and efficiency of data transfer are typically high priorities in such systems. Consumer multimedia systems and computer systems require high performance access to memories. Often, to ensure minimum cost of the system, the memories are operated very close to their optimal bandwidth. In other words, less expensive memory is typically lower performance, so to reduce system costs, developers use inexpensive memories and try to operate them as close as possible to their upper performance limit.
To approach this upper performance limit, typically complex memory access interfaces are used. For example, DRAM semiconductor memory access requires a RAS cycle to set the row address before successive column addresses for that row can be set to initiate data transfers. By using two or more banks of DRAMs, one bank can perform a RAS cycle while another performs data transfers. This concept is formalized by the use of SDRAM which is designed for such bank ping-ponging (for example, see NEC uPD4516161G5-A12-7JF specifications for 16 Mbit SDRAM).
To reduce complexity and cost of implementing memory access interfaces, the easiest way is to match the internal process timing to the external memory type or configuration. For example, in an MPEG-2 (see “IS 13818—Generic Coding of Moving Pictures and Associated Audio” by International Organization for Standardization, ISO MPEG Document, ISO-IEC/JTC1/SC2/WGI11 1994) video decoder integrated circuit using SDRAM as it's frame store, the motion compensation process which reads motion compensated macro-block pixel information from the SDRAM may generate row and column addresses with a timing similar to that required by the SDRAM. Thus, ping-ponging of banks is achieved by the motion compensation process. Matching internal process timing to the external memory type usually ties the internal architecture to the type or configuration of the external memory used. Thus, the internal generation of addresses by each internal process is designed specifically for a particular memory type or configuration.
There are several problems which this invention solves. An object of this invention is to permit memory accesses to occur sequentially as close together as possible in order to maximize the performance of memory accesses. Some memory systems require some kind of preprocessing to occur before the data transfer of a memory access can occur. For example, DRAM semiconductor memories require RAS and CAS cycles to initiate memory accesses. In a system with multiple DRAMs, it is possible to overlap in time the RAS cycles of one or more DRAMs with the CAS cycles of other DRAMs. Another example is SDRAM which contains multiple banks allowing for the overlap of one bank preprocessing with another banks data transfers. The control and optimization of timing for this overlap may result in complicated memory access controllers with complicated interfaces to the processes requiring access to the memory. An object of this invention is the implementation of a memory access controller with simple interfaces to processes requiring high performance access to memories. An object of this invention is the isolation of the processes requiring memory access from the control of the memory itself.
SUMMARY OF THE INVENTION
An object of the present invention is to permit the easy migration of a memory access controller to new or different memory types or configurations. Electronics products requiring memory migrate between types or configurations of memory as dictated by cost and performance considerations. Memory cost and performance changes rapidly as memory technology advances. Likewise, the applications which use memory must also change rapidly in order to take advantage of these changes. It is an object of this invention to permit the implementation of a memory access controller for one memory type to be easily modified to support alternative memory types. It is an object of this invention to permit the portability of a memory access controller between systems using different memory types or configurations.
An object of the present invention is to permit the easy migration of a memory access controller for use in different applications with different memory access requirements. A new application may use the memory differently from a previous application, but it is not cost effective to redesign the memory access controller, when instead a more general purpose memory access controller design can be used which does not require a lot of changes. It is an object of this invention to permit the implementation of a memory access controller for one set of memory access requirements and functionality to be easily modified to support alternative memory access requirements and functionality. It is an object of this invention to permit the portability of a memory access controller between different systems requiring different access to memory.
An object of the present invention is to reduce the size of memory access controllers without reducing the performance. For example, high performance and low cost is a requirement for consumer electronics.
For the purpose of solving the above-described problems, the memory access controller described herein was invented. Said memory access controller is used for converting memory access requests into memory access commands. Sequences of said memory access requests are input via a request input. An input logic accepts said memory access requests from said request input and demultiplexes said memory access requests into one or more requests, which are passed to corresponding need-makers. Said need-makers are used for determining needs, said needs indicating what memory access command is needed for each of said requests. Said needs are prioritized by a prioritizer resulting in prioritized needs. A need selector selects from said prioritized needs said memory access command. Said need selector comprises of a rule-checker which checks each said prioritized need against a set of rules and generates a corresponding prioritized command if said set of rules permits. Within said rule-checker, prioritized rule-checkers are used to check each of said prioritized needs against a set of rules generated by rule logic. A command output selector selects said memory access command from said prioritized commands. Sequences of said memory access commands are output via a command output.
The sequential memory access request input permits a simple interface between processes requiring access to memory and the memory, regardless of memory type or configuration. Multiple need-makers, prioritizers and prioritized rule-checkers are used to optimally overlap memory access preprocesses with the data transfers or other pre-processes. The prioritized commands which result from the prioritized rule-checkers are a set of possible commands for generating the control signals for memory accesses. They are effectively queued at the inputs to the command output selector until the first opportune moment when they can be issued to the memory. This results in optimal sequential output of memory access commands, thus permitting the maximum performance of memory access to be achieved. The processes which issue the memory access requests are not involved in the overlapping of memory access control commands, so they are isolated from many of the design details of the memory access itself. They simply send sequential m
Ellis Kevin L.
Greenblum & Bernstein P.L.C.
Matsushita Electric - Industrial Co., Ltd.
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