Memory access controller

Details Memory access controller Memory access controller

1998-10-27

2001-08-14

Lee, Thomas (Department: 2782)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S033000, C710S072000, C709S229000, C709S230000

Reexamination Certificate

active

06275877

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to direct memory access (DMA) control for a computer system and more particularly to a method and apparatus for utilizing a single dedicated memory controller to control all memory accesses in a computer system, both memory to memory accesses within the system and transfers between a system memory and various system peripherals.
BACKGROUND OF THE INVENTION
Many data processing operations in a computer system involve the movement of large amounts of data. Some of these data movements, including those involving various virtual memory or cache memory operations, involve the movement of data between various memories, generally random access memories, within the system, while other operations involve receiving or transmitting data through appropriate serial, parallel or other ports to system peripherals, which, for purposes of this invention, are considered to be various input/outputs (I/O) for the system. Such I/Os include, but are by no means limited to, printers, displays, modems, disc drives, fixed or variable length packetized data channels such as Ethernet, HDLC or token ring, optical disc drive, floppy drive, etc. An external processor may also require access to at least a selected portion of a system memory. Transfers of data between a system peripheral and a system memory, or between system memories, is complicated by the fact that the peripheral/memories frequently operate at different speeds, requiring buffering of data to effect efficient transfer, and that the peripherals/memories may have different format protocols.
In current systems, the burden of controlling the transfer of data between system memories and between peripherals and a system memory generally falls on the system processor. In some applications, the processor can spend a majority of its time handling such memory transfers, significantly reducing the capacity of the processor to perform other functions. The burden on the processor of controlling memory accesses thus significantly reduces the processing speed and efficiency of a given computer system and results in a significant reduction in the volume of work which the processor can perform. While various direct memory access (DMA) controllers have been proposed for reducing the DMA burden on a system processor, these controllers have generally been useful for only a single channel (i.e., the interfacing of a memory in a single direction with a peripheral or with another system memory) and have therefore dealt with only a portion of the problem. In order to deal with all modes of data transfer in a given system, a separate DMA controller of these types is required for each channel. Since a system may contain ten or more channels, existing controllers require significant circuitry dedicated to the DMA function, resulting in system boards of a size and cost which may not be acceptable for many applications.
A need therefore exists for an improved DMA controller which is capable of independently or substantially independently handling all, or at least substantially all, transfers of data between system memories, and between various peripherals and system memory with minimum processor involvement, thereby freeing the processor from the burden of performing DMA functions, and permitting dramatic increases in the volume of work available from the processor, without requiring significant system circuitry for performing the DMA function so as to minimize both the size and cost burden of this function.
Another problem in performing DMA functions is that memory buffers are typically of a fixed size, while data coming in from various packetized data channels, such as Ethernet or HDLC, can be of variable length. Normally the buffer length in the memory for receiving such variable length packetized data has to be large enough to receive the largest packets, which packets may be many times the size of the smallest packets transmitted, for example, 8 to 16 times the size of the smallest packets. This means that significant memory space is generally wasted when variable length packetized data is transferred into memory and that far more memory space must be allocated to receiving such data that would be the case if such variable length data where more efficiently stored. However, the housekeeping burden in more efficiently storing such variable length data has heretofore been such that, in most applications, no effort is made to more efficiently store such data. In the rare situations where such efforts are made, the added processing burden involved in doing such transfers further reduces processor availability for performing other functions.
A need therefore also exists for a DMA controller which facilitates the more efficient storage of variable length packetized data in system memory without requiring substantial processing, and in particular, with little if any added processing burden on the system processor.
SUMMARY OF THE INVENTION
In accordance with the above, this invention provides an access controller for a computer system memory, at least portions of which are accessible through a plurality of channels. The controller includes a context memory storing information relating to the current state of each channel, a component utilizing context memory information for a channel to control a memory access for the channel, at least a portion of such component being time shared by the channels, and a channel arbiter which selects the channel for which the component provides access control at a given time. The channel selection by the arbiter is preferably based on priorities for each channel stored in the context memory in a selected arbitration algorithm. The arbiter may scan the channels in a selected sequence each time channel selection is performed, highest priority channels being included in each scan, and channels having successively lower priorities being scanned at successively longer intervals, a channel being moved to the bottom of the scanned sequence after being selected by the channel arbiter.
The context memory may include a context buffer containing selected information on each required access transaction for each channel. The context buffer may contain a buffer descriptor for each access transaction, the descriptor containing a starting address indicator in system memory for the transaction, and a length indicator for data involved in the access transaction. Each buffer descriptor may also include a status indication for the access to which the descriptor relates and may also include at least one bit indicating that the buffer descriptor is the last descriptor of a selected group of descriptors. Such bit may for example include a wrap bit, the component performing accesses for a channel based on successive buffer descriptors until access is performed for a descriptor for which a wrap bit is present, the component returning to an initial buffer descriptor for the channel after an access involving the wrap bit-containing descriptor. Each buffer descriptor may also include a full bit (F-bit) which is set when the corresponding buffer is fill, the component not attempting to perform a read access to a buffer for which the F-bit is not set or a write access to a buffer for which the F-bit is set. Finally, each buffer descriptor may include an interrupt or I-bit, the controller issuing an interrupt to a system CPU after completion of an access transaction for which the corresponding descriptor has the I-bit present.
The context memory may also include configuration registers for each channel. One of the configuration registers for each channel may identify the start address for the buffer descriptors for the corresponding channel, and another of the configuration registers may be a control register having fields which control various functions. In particular, the control register may contain a priority field, the priority indicated by the priority field being a factor in channel selection by the channel arbiter, a field indicating a mode of memory access to be performed by the channel, a field indicating a quanti

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