Memory access control device with prefetch and read out block le

Details Memory access control device with prefetch and read out block le Memory access control device with prefetch and read out block le

1996-10-15

1998-05-12

Lane, Jack A.

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

711154, 711213, G06F 1200

Patent

active

057522723

ABSTRACT:
A memory access control device capable of reducing the cache miss penalty and taking an advantage of the DRAM with a high transmission bandwidth. In this device, a high speed memory for storing block data read from the memory device is provided, Then, when an access request is received from the master device, data requested by the access request is returned from the high speed memory to the master device whenever the data requested by the access request are contained in the block data stored in the high speed memory. Otherwise new block data of a variable block length to be stored in the high speed memory is read from the memory device according to the access request received from the master device. The block data includes prefetch data which have a possibility for being requested by a next access request from the master device. The device may include an access continuity judging unit for judging an access continuity for memory accesses made by the master device such that the read out block length of the new block data is controlled according to the access continuity.

REFERENCES:
patent: 4315312 (1982-02-01), Schmidt
patent: 4489378 (1984-12-01), Dixon et al.
patent: 4547849 (1985-10-01), Louie et al.

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