Memory access control circuit

Details Memory access control circuit Memory access control circuit

1998-02-17

2000-08-08

Yoo, Do Hyun

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

711164, 713200, G06F 1200

Patent

active

061015865

ABSTRACT:
For realizing a memory access control circuit giving a high degree of protection against a fraudulent access, an instruction fetch address register 14 holds the value of a program counter 11, a first area table 15 holds an address of a region to be protected in a memory, and a second area table 16 holds an address of an instruction allowed to access to the region to be protected. An access detecting circuit 17 compares an address of an access destination obtained as the result of an instruction decoding, with the address of the first area table 15, in order to discriminated whether or not the instruction is an instruction accessing to the region to be protected. When it is detected that the instruction is an instruction accessing to the region to be protected, a comparing circuit 18 compares the address of the instruction fetch address register 14 with the address of the second area table 16, in order to discriminated whether or not the instruction is read out from an area allowed to access to the region to be protected. If it is judged that instruction is read out from an area unallowed to access to the region to be protected, the comparing circuit 18 outputs an inhibiting signal, thereby to inhibit a fraudulent access.

REFERENCES:
patent: 4087856 (1978-05-01), Attanasio
patent: 4521852 (1985-06-01), Guttag
patent: 4521853 (1985-06-01), Guttag
patent: 4590552 (1986-05-01), Guttag et al.
patent: 4603381 (1986-07-01), Guttag
patent: 4875156 (1989-10-01), Tanagawa et al.
patent: 5600818 (1997-02-01), Weikmann

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