Memory access collision avoidance scheme

Details Memory access collision avoidance scheme Memory access collision avoidance scheme

2005-07-05

2005-07-05

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S104000, C711S168000, C711S150000, C365S230050

Reexamination Certificate

active

06915400

ABSTRACT:
A method and a circuit for avoiding memory access collisions during asynchronous read-write access to a single-port RAM (SPRAM) are described. Serial write access by means of a serial interface and read access with a read strobe from an independent read device are generated asynchronously. Prerequisites for the implementation are: firstly, use of a serial interface providing a serial clock signal; secondly, write access to SPRAM has to occur at the end of serial transmission; thirdly, a write strobe impulse has to be short compared to the original read strobe. Energy saving is achieved by guaranteeing only one regular read strobe, even when multiple write accesses occur during one read access. The read strobe signal can therefore be used also for control of an LCD backplane counter.

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