Static information storage and retrieval – Read/write circuit – Testing
Patent
1997-10-23
1999-06-08
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Testing
36523003, G11C 1300
Patent
active
059109238
ABSTRACT:
Testing of an integrated circuit having arrays of memory cells occurs by writing to all of the arrays at the same time. Normal writing occurs only to one array. Additional test data bus leads on the chip carry test data signals from selected arrays to comparison circuits. The outputs of the comparison circuits flow to the output circuits of the chip. This achieves writing test data to four times the number of arrays as in a normal write and reading test data from twice the number of arrays as in a normal read operation.
REFERENCES:
patent: 5499216 (1996-03-01), Yamamoto
Brown Brian L.
Brown David R.
Norwood Roger D.
Penney Daniel B.
Bassuk Lawwrence J.
Donaldson Richard L.
Fears Terrell W.
Texas Instruments Incorporated
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