Memory access circuit and method for reading and writing...

Static information storage and retrieval – Systems using particular element – Flip-flop

Reexamination Certificate

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C365S230060, C365S233100, C326S037000

Reexamination Certificate

active

06917536

ABSTRACT:
A read operation and a write operation are synchronized via one port of a memory cell to avoid contention between such operations while doubling the bandwidth of such operations. Data is read from and data is written to a memory cell through a single port of the cell. A memory cell having a port is provided, and a clock signal is also provided for clocking the memory cell. The clock signal has a leading edge and a lagging edge within a clock signal cycle. During a single clock cycle, an enable read control signal is asserted in response to the clock signal, and an enable write control signal is asserted in response to the clock signal. In response to the enable read control signal, read data stored within the memory cell is read through a port of the cell. In response to the enable write control signal, write data is written to the memory cell through the port.

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Xilinx, Virtex-II 1.5V, Advance Product Specification sheets, dated Oct. 2, 2001.

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