Median spaced dummy cell layout for MOS random access memory

Details Median spaced dummy cell layout for MOS random access memory Median spaced dummy cell layout for MOS random access memory

1978-06-15

1980-03-25

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Differential sensing

365149, 365205, G11C 700

Patent

active

041953576

ABSTRACT:
A random access memory device of the MOS integrated circuit type employs an array of rows and columns of one-transistor storage cells with bistable sense amplifier circuits at the center of each column. A dummy cell is connected to each column line half and is addressed when a memory cell on the opposite side of the sense amplifier is addressed by one of the row lines. Time delay is made more equal by placing the dummy cells at about the center of each column line half. The signals on the column line halves from the dummy cell and from the selected memory cell will reach the sense amplifier at about the same time, on average.

REFERENCES:
patent: 4038646 (1977-07-01), Mehta et al.
patent: 4050061 (1977-09-01), Kitagawa
patent: 4117545 (1978-09-01), Inadachi
patent: 4118794 (1978-10-01), Mizuno et al.

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