Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses
Reexamination Certificate
2008-07-01
2008-07-01
Bragdon, Reginald G. (Department: 2189)
Electrical computers and digital processing systems: memory
Address formation
Generating a particular pattern/sequence of addresses
C711S154000, C711S218000
Reexamination Certificate
active
07395407
ABSTRACT:
The present invention comprises a data access pattern interface that allows software to specify one or more data access patterns such as stream access patterns, pointer-chasing patterns and producer-consumer patterns. Software detects a data access pattern for a memory region and passes the data access pattern information to hardware via proper data access pattern instructions defined in the data access pattern interface. Hardware maintains the data access pattern information properly when the data access pattern instructions are executed. Hardware can then use the data access pattern information to dynamically detect data access patterns for a memory region throughout the program execution, and voluntarily invoke appropriate memory and cache operations such as pre-fetch, pre-send, acquire-ownership and release-ownership. Further, hardware can provide runtime monitoring information for memory accesses to the memory region, wherein the runtime monitoring information indicates whether the software-provided data access pattern information is accurate.
REFERENCES:
patent: 2006/0248281 (2006-11-01), Al-Sukhni et al.
Shafi Hazim
Shen Xiaowei
Bragdon Reginald G.
F. Chau & Associates LLC
International Business Machines - Corporation
Vo Thanh D
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