Mechanism to store reordered data with compression

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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Details

C711S100000, C711S133000, C711S154000, C711S165000, C711S170000

Reexamination Certificate

active

10747470

ABSTRACT:
According to one embodiment a computer system is disclosed. The computer system includes a central processing unit (CPU), a cache memory coupled to the CPU and a cache controller, coupled to the cache memory. The cache memory includes a plurality of compressible cache lines to store additional data. The cache controller reorders a cache line after each access to the cache line prior to the compression of the cache line into a compressed cache line.

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PCT Search Report, PCT/US2004/043233, mailed Mar. 21, 2005.

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