Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-01-21
2002-05-14
Ray, Gopal C. (Department: 2181)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S006130, C713S320000, C713S321000, C713S323000, C713S324000, C711S112000
Reexamination Certificate
active
06389556
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to power management in computer systems and more particularly to entry and recovery from sleep states.
2. Description of the Related Art
One goal of the personal computer industry is to provide personal computers (PCs) that act like any other home appliance. In other words, the PC should function in a predictable and reliable fashion, just like other home appliances. A typical mindset is to expect VCR-like behavior from a PC. When a VCR is switched off and is later turned on, the VCR typically starts playing video from the same spot at which it was stopped. If power is removed from a VCR that is “off”, and power is applied back later, the behavior of the VCR does not change.
One approach to managing power in computer systems is described in the Advanced Configuration and Power Interface (ACPI) Specification (revision 1.0a dated Nov. 19, 1998), which is incorporated herein by reference. The ACPI specification identifies multiple system power states for PCs. In particular, the ACPI specification identifies multiple sleeping states that have varying power requirements and can have varying wake-up latencies. One of the states (S
3
), also called suspend to RAM (STR), allows the system to enter a low power state but resume activity without any information being lost. Once activity is resumed, after the recovery latency, the user sees the system as if it never entered the low power state. In order to accomplish that, system state information, such as all the system configuration data (e.g., chipset configuration information) is saved into system memory, thus saving the “system context.” Once that is done, power to most of the system components (except system memory), is turned off, resulting in a significant reduction in the system power consumption. In the S
3
state power to the central processing unit (CPU) and most other system components (e.g., the display) is turned off. Those devices that can “wake-up” the system, e.g. the mouse and its interface, the modem and its interface, are supplied sufficient power to be able to alert the system to a wake-up event.
When a PC system is not being used, it is customary, after a period of inactivity, to put the computer system in the S
3
state so that system power consumption can be reduced. While in the S
3
state, the PC appears to be off to the end user, meaning that no lights are on, and fans are not working. When a wake-up event occurs, e.g., when modem activity is detected, a keyboard key is pressed, or mouse movement is detected, the system context is restored using the system configuration data in system memory and the user sees the PC in exactly the same state in which the PC was in before it entered the S
3
state. The wake up latency to transition from S
3
→S
0
(the operating state) of five seconds is considered acceptable when the PC is turned “on”. However, if there is a power failure, or if the PC is unplugged from the wall socket while in the S
3
state, all state information that was being stored in system memory is lost, and the system needs to reboot when power is reapplied. That type of behavior is not desirable to the average user.
Another system sleep state (S
4
), also called suspend to disk (STD), allows all of the system configuration data and an image of system memory to be saved to a non-volatile medium such as a hard disk. That sleep state allows system power to be removed from the entire system (including the system memory), resulting in lower power consumption than that in the S
3
state. When the system needs to wake up, the system state information is restored from the system disk. The wake up sequence from S
4
typically takes a much longer time compared to wake up from S
3
, because of the relative large disk access time.
The problem of data volatility in system memory can be addressed by always placing the system in the suspend to disk (S
4
) state. However, that results in unacceptably long wake up times that would be undesirable to the average user. It would be desirable to address to problem of data volatility without always paying the penalty of long wake up latencies.
SUMMARY OF THE INVENTION
Accordingly, an improved sleep state has been discovered that provides the benefits of low latency wake up for normal situations, but also provides the ability to wake up in the event that system memory is corrupted during the sleep state due to, e.g., a power failure during that sleep state. Before entering the sleep state, the software operating on the computer system saves system state information relating to the computer system into system memory. In addition, the computer system saves that state information and an image of system memory to non-volatile memory such as a disk drive. The computer system may set a flag in a non-volatile memory location indicating that the computer system is in a special sleep state. At that point power is removed from most of the computer system but power is maintained to the system memory under normal conditions. In response to a wake-up event, the computer system determines if the contents of the system memory have been corrupted. If the contents of the system memory is valid, the state information in the system memory is used to restore the computer system. If however, the contents of the system memory is not valid, the state information and system memory image saved in the non-volatile memory is used to restore the computer system.
REFERENCES:
patent: 5765001 (1998-06-01), Clark et al.
patent: 6145068 (2000-11-01), Lewis
patent: 6243819 (2001-06-01), Jung
patent: 6243831 (2001-06-01), Mustafa et al.
Intel/Microsoft/Toshiba, “Advanced Configuration and Power Interface Specification”, Revision 1.0a, Nov. 19, 1998, particularly sections 9 through 9.3.4.
Advanced Micro Devices , Inc.
Ray Gopal C.
Zagorin O'Brien & Graham LLP
LandOfFree
Mechanism to prevent data loss in case of a power failure... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Mechanism to prevent data loss in case of a power failure..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Mechanism to prevent data loss in case of a power failure... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2850737