Mechanism to minimize failure in differential sense amplifiers

Details Mechanism to minimize failure in differential sense amplifiers Mechanism to minimize failure in differential sense amplifiers

2002-02-11

2003-06-03

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S205000, C365S230060

Reexamination Certificate

active

06574160

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to memory devices; more particularly, the present invention relates to sense amplifiers.
BACKGROUND
In the design of differential sense amplifiers for memories, extreme care is taken to make sure that all device and parasitic parameters match perfectly on each side of the amplifier. Differential sense amplifiers are designed to detect minute differences in either voltage or current between true and false signals from information being read from a memory cell.
If there is any sort of mismatch between the true and false sides of the amplifier, the resulting output may incorrectly flip in the opposite direction to the value that needs to be read. In other words, the output may read a logic 1 instead of the actual logic 0 that is stored in the particular memory cell, or vice versa.
Typically the only way to fix such an occurrence is to introduce more delay into the signal that evaluates the sense amplifier, thus causing reduction in performance. In addition, since the signal is usually self-timed, rather than cycle dependent, if the mismatch in silicon is greater than expected during the time of the design, the amplifier will not operate at any frequency of the system clock.
In newer small-scale device technologies, a phenomenon called negative bias temperature instability (NBTI) causes the threshold voltage of PMOS devices to increase by a certain voltage level depending upon the historical amount of voltage bias that is observed between the gate and source/drain nodes of a device.
In the case of sense amplifiers, if the same data value is read repeatedly, one PMOS device of the amplifier will see the maximum NBTI voltage threshold shift, while the other PMOS device observes no shift. Consequently, a mismatch between the true and false sides of the amplifier will likely occur. As described above, such a mismatch causes failures in reading data from a memory.
SUMMARY
According to one embodiment, a computer system is disclosed. The computer system includes a microprocessor, a memory controller coupled to the microprocessor and a memory coupled to the memory controller. The memory includes a differential sense amplifier that receives a data input and a complementary data input; and a switching mechanism, coupled to the amplifier, that switches the data input and the complementary data input to minimize a Negative Bias Temperature Instability (NBTI) effect on the amplifier.


REFERENCES:
patent: 5539700 (1996-07-01), Kawahara et al.
patent: 5710737 (1998-01-01), Komiya et al.
patent: 6101141 (2000-08-01), Schoniger et al.
patent: 6442099 (2002-08-01), Kant et al.

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