Mechanism to improve performance in a multi-node computer...

Details Mechanism to improve performance in a multi-node computer... Mechanism to improve performance in a multi-node computer...

2005-03-01

2005-03-01

Fleming, Fritz (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output access regulation

C709S201000, C709S223000, C712S032000

Reexamination Certificate

active

06862634

ABSTRACT:
In a distributed multi-node computer system each switch provides routing of data packets between CPU nodes, I/O nodes, and memory nodes. Each switch is connected through a corresponding I/O node to a network interface controller (NIC) for transferring data packets on a network. Each NIC is memory-mapped. Part of the system address space forms a send window for each NIC connected to a corresponding switch. A mechanism for controlling data packets transmission is defined such that each CPU write to a NIC send window is atomic and self-defining, i.e., it does not rely on immediately preceding write to determine where the data packet should be sent. Using “address aliasing”, CPU writes to the aliased part of the NIC send window are always directed to the NIC connected to the same switch as the CPU which did the write.

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