Mechanism to extend computer memory protection schemes

Electrical computers and digital processing systems: memory – Address formation – Address mapping

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C711S208000, C711S156000

Reexamination Certificate

active

06643759

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to the field of memory management in within a computing system, and more particularly to an apparatus and method for extending the kinds of access protections for virtual memory pages beyond those provided for by page protection mechanisms within an existing translation lookaside buffer architecture.
2. Description of the Related Art
Early computing systems executed application programs that were composed especially to run on those systems. The programs consisted of a sequence of instructions that were loaded into the memory of the computing system at the time of execution. Address logic within the computing system generated a memory address each time an instruction was fetched from the memory for execution. Access logic within the computing system placed the memory address out on a memory address bus and the memory provided the contents of the memory location corresponding to the memory address for execution by the computing system. In addition to program instructions, the early computing systems employed memory locations to temporarily store data that was used by application programs. And like the retrieval of program instructions for execution, the storage and retrieval of program data involved the generation of memory addresses that corresponded to data memory locations.
The memory addresses generated by the address logic were directly routed to the early computing systems' memory busses to access corresponding memory locations. Hence, to access location 10513BC7h in memory required that the address logic generate address 10513BC7h and issue this address to the memory bus. But stated differently, it also is true that when the address logic generated address 10513BC7h, the memory location to which this address corresponded was also location 10513BC7h.
It is intuitive to observe that a direct, one-to-one correspondence between memory addresses generated by a program executing on an early computing system and locations in the computing system's memory was quickly deemed disadvantageous from many standpoints. First, in order to execute a wide variety of application programs, it was required that the early computing system always provide memory that spanned the full address range of the system. Second, such correspondence unnecessarily coupled the architecture of the computing system to the tools that were used to produce and execute programs on the system. For instance, programs required significant changes to enable the programs to execute on computing systems that exhibited different memory ranges and constraints. And finally, as computers progressed to the point of providing time-share (i.e., multi-tasking) operating systems, performance degradations were observed since all memory management and protection functions had to be performed by the operating systems.
Virtual memory management techniques were developed during the mid-1970's specifically to address the above-noted problems. In essence, a virtual memory “manager” within a computing processing unit (CPU) serves as an intermediary between address generation logic in the CPU and access logic that accesses memory locations. Under a virtual memory management scheme, a “virtual address” generated by the address logic is “translated” according to a predefined and configurable mapping strategy into a “physical address” that is placed on the memory bus to access a corresponding memory location. Hence, virtual memory management overcomes the above-noted limitations of one-to-one correspondence.
Virtual memory management techniques continue to provide benefits that enable the operating system of a computing system to effectively control where application programs are loaded and executed from memory, in addition to providing a means whereby memory can be assigned to a program while it is running and then released back into the memory pool when the memory is no longer required by the program. Most present day virtual memory management units divide a system's address space into equal-sized chunks called memory pages. To access a memory page requires translation of the upper bits of a virtual address; the lower bits of the virtual address are not translated and merely represent an offset into a page.
Virtual memory management not only applies to the locations associated with memory, but also to the properties, or attributes, associated with those locations. For instance, a virtual page may be designated as read-only so that data writes to locations in the page can be precluded.
The virtual-to-physical address mapping information, along with information specifying the attributes of virtual memory pages, are stored in a designated area of memory known as a page table. Generally speaking, a page table contains one entry for each virtual memory page within the address space of a CPU. Hence, for each memory access, it is required that the page table entry associated with the access be retrieved from the page table so that the virtual address can be translated into a physical address and so that access privileges can be determined.
Translation lookaside buffers (TLBs) have been incorporated into CPU designs to store frequently used page table entries within a CPU so that a memory access is not required each time an address is generated. A TLB is a very fast memory providing storage for a number of page table entries. TLBs are designed to be efficient and fast because they typically lie in the critical timing path of a CPU. Accordingly, only those bits that are essential to the translation of addresses and specification of memory page attributes are provided in a page table entry within a TLB.
TLBs are streamlined to support rapid access for the translation of addresses. As a result, however, the structure of a given TLB is quite static, yielding little or no room for expansion. Hence, if it is desired to update the design of a CPU to incorporate a newly developed or expanded set of memory access protection schemes, then it is highly probable that the design of the CPU's TLB must be modified to provide for expression of the access restrictions at the virtual page level. But for CPU's that have relegated a significant portion of their virtual memory management tasks to operating system software, changing the structure of an existing TLB creates incompatibilities with the operating system software-the operating system must be updated in order to provide for memory management according to the new/expanded access restrictions.
A significant market segment is lost, however, when an upgraded CPU becomes no longer compatible with an older operating system and its application programs. CPU manufacturers desire, at least, that CPU upgrades retain compatibility with older software. But compatibility retention in the case of a software managed TLB architecture implies that the number of access privileges that are provided for in a upgraded design be controlled by the existing TLB structure.
Therefore, what is needed is an apparatus that allows extended access protection schemes to be provided via an existing TLB design, where the structure of the TLB is maintained for compatibility with a legacy access protection protocol.
In addition, what is needed is a mechanism for extending the access restrictions of virtual memory pages that utilizes an existing TLB structure.
Furthermore, what is needed is a CPU apparatus that allows more kinds virtual memory page access privileges to be prescribed over that afforded by an existing TLB structure, where the TLB structure also is backwards-compatible with older operating system software.
Moreover, what is needed is a method for extending virtual memory page access protections of an existing TLB, but which defaults to states that can be interpreted according to a legacy access protection protocol.
SUMMARY OF THE INVENTION
The present invention provides a superior technique for extending the kinds of access protections afforded to virtual memory pages beyond that provided for by an existing tran

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Mechanism to extend computer memory protection schemes does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Mechanism to extend computer memory protection schemes, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Mechanism to extend computer memory protection schemes will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3165218

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.