Mechanism to expand address space of a serial bus

Details Mechanism to expand address space of a serial bus Mechanism to expand address space of a serial bus

1999-07-07

2003-02-25

Wong, Peter (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus expansion or extension

Reexamination Certificate

active

06526464

ABSTRACT:

BACKGROUND
The invention relates generally to serial bus operations within a computer system and more particularly, but not by way of limitation, to a mechanism to expand the number of devices that may be addressed on a serial bus.
Referring to
FIG. 1
, many current computer systems
100
incorporate serial communication bus
102
to facilitate system initialization, system administration, and power management operations. For example, serial bus controller
104
may use serial bus
102
to communicate with processor
106
, second level cache memory
108
, system memory
110
, input-output (I/O) controller
112
, power management devices
114
(e.g., clock generation circuitry and/or thermal control components such as fan units), and other system devices
116
. As indicated, system components may also communicate via system bus
118
. Illustrative serial busses include the Inter-Integrated Circuit (I
2
C) bus sponsored by Phillips Semiconductor and the System Management Bus (SMBus) sponsored by Intel Corporation.
One use of serial bus
102
is to retrieve device configuration data from, for example, processor and system memory electrically erasable programmable read only memory (EEPROM) during system startup and/or reset operations. Another use of serial bus
102
is to monitor and control power management devices (e.g., component
114
). For example, thermal sensors may communicate with a thermal monitoring routine (executed by processor
106
or, perhaps, a separate microcontroller included within device
114
or
116
) which, in turn, control clock generation and/or fan circuitry.
The address space of serial bus
102
(i.e., the range of possible addresses) is generally limited both by definition and by practice. For example, current embodiments of the I
2
C and SMBus use a 7-bit address field which, when reserved addresses are accounted for, provide less than 100 possible addresses. Further limiting serial bus address space is the practice of many device manufacturers to preset one or more of their configuration EEPROM address lines to fixed values (e.g., configuration EEPROM associated with processor
106
, second level cache
108
, or system memory
110
). In combination, and as a result, system designers are often limited to 8, or fewer, devices of the same type on serial bus
102
. Thus, it would be beneficial to provide a mechanism to expand the number of devices that may be addressed by a serial bus.
SUMMARY
In one embodiment the invention provides computer system having a serial bus controller coupled to a primary serial bus, connector means adapted to receive at least one device having a serial bus interface, and a gating device coupled to the primary serial bus and the serial bus interface of the at least one device, the gating device having a control input, the gating device adapted to selectively couple and uncouple the at least one device to the primary serial bus in accordance with the control input. By selectively enabling different gating devices, the effective serial bus address space of the computer system may be expanded indefinitely.
In another embodiment the invention provides a method to selectively couple and uncouple a device to a primary serial bus. The method includes determining if a serial sub-bus exists and, if it does, selectively coupling the serial sub-bus to the primary serial bus, accessing a device coupled to the serial sub-bus, and deselecting the serial sub-bus to uncouple the serial sub-bus from the primary serial bus. Methods in accordance with the invention may be stored in any media that is readable and executable by a programmable control device.


REFERENCES:
patent: 5581541 (1996-12-01), Whetsel
patent: 5742847 (1998-04-01), Knoll et al.
patent: 5875353 (1999-02-01), Whetsel
patent: 6161157 (2000-12-01), Tripathi et al.
patent: 6205502 (2001-03-01), Endo et al.

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