Mechanism for sharing data cache resources between data prefetch

Details Mechanism for sharing data cache resources between data prefetch Mechanism for sharing data cache resources between data prefetch

1998-08-03

2000-09-12

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711213, G06F 1208

Patent

active

061192031

ABSTRACT:
A data processing system (10) provides a mechanism for choosing when the data stream touch (DST) controller (300) is allowed access to the data cache and MMU (50). The mechanism uses a count value to determine at what point in program execution the DST controller (300) is allowed to interrupt normal load and store accesses. This allows DST prefetches to be optimized for maximum performance of the data processing system (10).

REFERENCES:
patent: 5117490 (1992-05-01), Duxbury et al.
patent: 5828860 (1998-10-01), Miyaoku et al.
patent: 5835967 (1998-11-01), McMahan
patent: 5896291 (1999-04-01), Hewitt et al.

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