Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
Reexamination Certificate
2006-09-12
2006-09-12
Fleming, Fritz (Department: 2181)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Scoreboarding, reservation station, or aliasing
C712S215000, C712S206000
Reexamination Certificate
active
07107433
ABSTRACT:
A mechanism for resource allocation in a processor, a method of allocating resources in a processor and a digital signal processor incorporating the mechanism or the method. In one embodiment, the mechanism includes: (1) categorization logic, associated with an earlier pipeline stage, that generates instruction type information for instructions to be executed in the processor and (2) priority logic, associated with a later pipeline stage, that allocates functional units of the processor to execution of the instructions based on the instruction type information.
REFERENCES:
patent: 3863225 (1975-01-01), Preiss
patent: 5651125 (1997-07-01), Witt et al.
Fleming Fritz
Hitt Gaines PC
LSI Logic Corporation
Meonske Tonia L.
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