Mechanism for reducing timing jitter in clock recovery scheme fo

Details Mechanism for reducing timing jitter in clock recovery scheme fo Mechanism for reducing timing jitter in clock recovery scheme fo

1993-01-25

1995-06-13

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375376, 3647241, 380 34, H04L 700, H04L 2536, H04L 2540

Patent

active

054250609

ABSTRACT:
Timing jitter in the clock recovery loop of a `blind` signal acquisition receiver employing a square law detector in a phase lock loop signal flow path is substantially reduced by adaptively adjusting the parameters of the loop's pre-filter, so as to compensate for conjugate antisymmetric components in the spectrum of the monitored signal of interest. The signal timing recovery signal processing mechanism includes a filter parameter adjustment operator which controllably sets the weighting parameters of a baseband prefilter, so that the filtered signal does not possess conjugate antisymmetry about the Nyquist frequency and the spectrum of the filtered signal is essentially conjugate symmetric.

REFERENCES:
patent: 4862484 (1989-08-01), Roberts
patent: 4953186 (1990-08-01), Levy et al.
patent: 5093847 (1992-03-01), Cheng

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