Mechanism for reducing latency of memory barrier operations on a

Details Mechanism for reducing latency of memory barrier operations on a Mechanism for reducing latency of memory barrier operations on a

1997-10-24

2000-07-11

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

711147, 711163, 709213, 709248, 712225, G06F 1300

Patent

active

060887710

ABSTRACT:
A technique reduces the latency of a memory barrier (MB) operation used to impose an inter-reference order between sets of memory reference operations issued by a processor to a multiprocessor system having a shared memory. The technique comprises issuing the MB operation immediately after issuing a first set of memory reference operations (i.e., the pre-MB operations) without waiting for responses to those pre-MB operations. Issuance of the MB operation to the system results in serialization of that operation and generation of a MB Acknowledgment (MB-Ack) command. The MB-Ack is loaded into a probe queue of the issuing processor and, according to the invention, functions to pull-in all previously ordered invalidate and probe commands in that queue. By ensuring that the probes and invalidates are ordered before the MB-Ack is received at the issuing processor, the inventive technique provides the appearance that all pre-MB references have completed.

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