Mechanism for providing measured power management...

Details Mechanism for providing measured power management... Mechanism for providing measured power management...

2007-10-02

2007-10-02

Perveen, Rehana (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C327S113000

Reexamination Certificate

active

10806041

ABSTRACT:
An apparatus and method are provided that enable a computing device to make graceful power state transitions that do no impose unnecessary power surge compensations requirements on associated power sources. The apparatus has power control logic that is configured to determine if the computing device is to enter a low power state. The power control logic includes a plurality of stop signals. Each of the plurality of stop signals sequentially indicates that a corresponding clock signal be stopped, where the corresponding clock signal is operatively coupled to a corresponding sector logic element within the computing device.

REFERENCES:
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patent: 5724591 (1998-03-01), Hara et al.
patent: 6115763 (2000-09-01), Douskey et al.
patent: 2003/0196127 (2003-10-01), Olsen
patent: WO0022501 (2000-04-01), None

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