Mechanism for PCI I/O-initiated configuration cycles

Details Mechanism for PCI I/O-initiated configuration cycles Mechanism for PCI I/O-initiated configuration cycles

2005-07-05

2005-07-05

Auve, Glenn A. (Department: 2112)

Electrical computers and digital data processing systems: input/

Intrasystem connection

System configuring

C710S010000, C710S314000

Reexamination Certificate

active

06915365

ABSTRACT:
Methods and apparatus for inbound PCI configuration cycles are disclosed. By definition, PCI bridges block upstream progress of configuration cycles initiated by a PCI bus master on their secondary buses. In the described embodiments, a PCI bus master can execute a configuration cycle despite this limitation, by converting the configuration cycle command to Memory Read and Write commands that a PCI bridge will forward upstream. The PCI bus master writes the address of a target configuration register to a first predefined address, and pushes or pulls data from that target register by subsequently initiating a memory access to a second predefined address. A platform chipset is designed to recognize Memory Read and Write accesses to the predefined addresses as relating to an inbound configuration cycle. When a memory access to the second address is received, the chipset uses the information stored at the first address to form and execute a configuration cycle on behalf of the downstream PCI bus master.

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