Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2000-02-07
2004-04-27
Lefkowitz, Sumati (Department: 2189)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S305000, C710S306000, C710S110000, C710S314000
Reexamination Certificate
active
06728808
ABSTRACT:
TECHNICAL FIELD
The present invention generally pertains to the field of the peripheral component interconnect (PCI) bus architecture. More particularly, the present invention relates to the field of transaction retries over a PCI bus.
BACKGROUND ART
Computers are useful functional devices which are fabricated in a variety of sizes ranging from computers which occupy large office space down to computers which are held in one's hand. These varying sizes of computers also perform an extremely wide variety of useful operations, depending on the software which is installed within their particular memory storage device. For example, computers can manage numerous financial transactions of a bank, control the fabrication of items ranging from automobiles down to integrated circuit chips, store addresses and telephone numbers of business and personal acquaintances, enable someone to produce and edit documents, along with transmitting and receiving data over a network such as the internet.
It should be appreciated that within a typical computer system there exists one or more bus architectures which are used to convey signals and information between distinct internal components of the computer system. For example, one or more bus architectures are typically used to connect a central processing unit (CPU) of the computer system to one or more of its memory storage devices. Additionally, the CPU is also usually connected to varying input/output components of the computer system by utilizing one or more different bus architectures. Therefore, when the computer system executes its programming, useful information and signals are able to be communicated between the CPU, memory storage devices, and diverse input/output components of the computer system.
In order to increase the functionality and usefulness of a computer system, varying peripheral devices are typically connected to it, such as a small computer systems interface (SCSI) host bus adapter, local area network (LAN) adapter, video adapter, graphics adapter, and the like. Additionally, these types of peripheral devices are also connected to the CPU, memory storage devices, and other components of the computer system by using one or more different bus architectures. It should be understood that over time the computer and electronics industry has developed several different types of bus architectures. One of the most widely used and widely supported bus architectures in the computer and electronics industry is the peripheral component interconnect bus architecture, commonly referred to as the PCI bus architecture. The PCI bus was developed in order to provide a high speed and low latency bus architecture from which a wide variety of systems can be developed. As part of the PCI bus architecture, a definitive set of rules and protocols were established for PCI agents connected to a PCI bus in order to standardize the manner of accessing, utilizing, and relinquishing the PCI bus. One of the purposes for the PCI standard is to maximize the data transfer bandwidth of the PCI bus. It should be appreciated that the set of rules and protocols of the PCI bus architecture are set forth in an industry standard PCI specification.
There are disadvantages associated with the PCI bus architecture. For instance, there are situations where the availability of the PCI bandwidth is substantially reduced, thereby limiting access to other requesting PCI bus master devices connected thereto. Specifically, one example of this occurs when a PCI bus master device issues a transaction to a target device over a PCI bus and the target device is currently unable to fulfill the requested transaction. As such, the target device issues a retry signal to the master device over the PCI bus. The receipt of the retry signal causes the master device to relinquish control of the PCI bus so it may be used by other PCI bus master devices. Under the rules of the PCI specification, the master device continues to reissue the transaction to the target device until the transaction is finally completed by the target device. As such, the master device typically arbitrates for and acquires the PCI bus as soon as possible in order to reissue the transaction to the target device for a second time. If the target device is still not ready to fulfill the requested transaction (which can often happen), the target device again issues a retry signal to the master device causing it to relinquish control of the PCI bus. This process continues until the transaction is eventually completed by the target device.
Given that the PCI specification dictates that only one transaction can take place over a PCI bus at any given time, the PCI bus is tied up by the PCI bus master device continually reissuing the transaction to the target device. Therefore, the availability of the PCI bandwidth is substantially reduced, thereby limiting access to other requesting PCI bus master devices connected thereto.
DISCLOSURE OF THE INVENTION
Accordingly, a need exists for a method and system for optimizing transaction signal retries between a PCI bus master device and a target device communicatively coupled by a PCI bus. The present invention provides a method and system which accomplishes this functionality along with other benefits.
Specifically, one embodiment of the present invention provides a system which optimizes transaction retries issued by a PCI bus master device to a target device coupled to a PCI bus. The system includes a target device communicatively coupled to a PCI bus and able to issue a retry signal over the PCI bus. Furthermore, the system includes a PCI bus master device communicatively coupled to the PCI bus and able to issue a transaction signal to the target device over the PCI bus. Additionally, the system includes a retry timer circuit coupled to the PCI bus master device in order to respond when the PCI bus master device receives the retry signal issued by the target device over the PCI bus. The retry timer circuit causes the PCI bus master device to wait a fixed period of time before reissuing the transaction signal to the target device over the PCI bus. The fixed period of time is regulated by the retry timer circuit and is hardwired into the retry timer circuit.
In another embodiment, the present invention provides a system which is similar to the previous embodiment. Specifically, the system of the present embodiment includes a retry timer circuit coupled to the PCI bus master device in order to respond when the PCI bus master device receives the retry signal issued by the target device over the PCI bus. The retry timer circuit causes the PCI bus master device to wait a delay value before reissuing the transaction signal to the target device over the PCI bus. The delay value is regulated by the retry timer circuit and is stored by the retry timer circuit. It should be appreciated that the delay value stored by the retry timer circuit can be changed by the PCI bus master device and/or by a remote device (e.g., CPU).
In still another embodiment, the present invention includes a system which dynamically optimizes transaction retries issued by a PCI bus master device to a target device coupled to a PCI bus. The system also includes a target device and a PCI bus master device communicatively coupled to a PCI bus. Additionally, the system includes a latency determination circuit coupled to the PCI bus master device and able to determine a delay value equivalent to how much time expires between the PCI bus master device receiving a first retry signal from the target device and the target device finally fulfilling this transaction issued by the PCI bus master device. Moreover, the system includes a retry timer circuit coupled to receive the delay value from the latency determination circuit. The retry timer circuit is able to respond when the PCI bus master device receives a second retry signal over the PCI bus corresponding to a second transaction issued by the PCI bus master device. The retry timer circuit is also able to cause the PCI bus master device to wait the delay value before
3Com Corporation
Lefkowitz Sumati
Vu Trisha
LandOfFree
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