Mechanism for on-the-fly handling of unaligned memory accesses

Details Mechanism for on-the-fly handling of unaligned memory accesses Mechanism for on-the-fly handling of unaligned memory accesses

2006-07-11

2006-07-11

Vital, Pierre (Department: 2185)

Electrical computers and digital processing systems: memory

Address formation

Slip control, misaligning, boundary alignment

C712S244000

Reexamination Certificate

active

07076631

ABSTRACT:
Unaligned accesses to memory are circumvented by an address exception handler mechanism, which decodes an exception-triggering instruction, and reads from or writes to, in a byte-by-byte manner, addressed portions of memory which are unaligned with an addressing scheme through which accesses to memory may be performed, and thereby give rise to unaligned memory access exceptions. The handler simulates the execution of the instruction with reference to an exception stack frame, to which the contents of all registers at the time of the unaligned address exception are saved. This allows the handler to controllably define values that are restored into registers during the processor's execution of a general exception vector. After handling the exception, program execution transitions to the next instruction that directly follows the exception-causing instruction.

REFERENCES:
patent: 6772372 (2004-08-01), McKee et al.
patent: 6898697 (2005-05-01), Gao et al.
patent: 2004/0098556 (2004-05-01), Buxton et al.

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