Mechanism for managing offset and aliasing conditions within a c

Details Mechanism for managing offset and aliasing conditions within a c Mechanism for managing offset and aliasing conditions within a c

1996-10-31

1998-09-01

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711146, 711136, 711131, 711108, 364131, G06F 1200

Patent

active

058025677

ABSTRACT:
A cache memory having a mechanism for managing offset and aliasing conditions is disclosed. In accordance with a preferred embodiment of the invention, the cache memory comprises a first directory circuit, a second directory circuit, a multiple number of most recently used bits, and a multiple number of set/reset circuits. The first directory circuit, having multiple caches lines, is utilized to receive partial effective addresses. The second directory circuit is utilized to receive an output from the first directory circuit. A most recently used bit is associated with each cache line within the first directory circuit. The set/reset circuit, coupled to each of the most recently used bits, is utilized to set one of the most recently used bits to a first state while concurrently resetting the rest of the most recently used bits to a second state within a single cycle during an occurrence of an offset or aliasing conditions such that offset or aliasing conditions can be more efficiently managed.

REFERENCES:
patent: 4594651 (1986-06-01), Jaswa et al.
patent: 5602764 (1997-02-01), Eskandari-Gharnin et al.
patent: 5640534 (1997-06-01), Liu et al.

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