Electrical computers and digital data processing systems: input/ – Interrupt processing
Reexamination Certificate
2001-08-31
2004-08-17
Auve, Glenn A. (Department: 2111)
Electrical computers and digital data processing systems: input/
Interrupt processing
Reexamination Certificate
active
06779065
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to computer systems and, in particular to mechanisms for handling interrupts in computer systems that support concurrent execution of multiple threads.
2. Background Art
Modern high-performance processors are designed to execute multiple instructions on each clock cycle. To this end, they typically include extensive execution resources to facilitate parallel processing of the instructions. The efficient use of these resources may be limited by the availability of instructions that can be executed in parallel. The availability of instructions for parallel execution is referred to as instruction level parallelism (ILP). Instruction dependencies limit the ILP available in a single execution thread. If only one execution thread can be processed at a time, instruction throughput is reduced as well.
One approach to increasing instruction throughput is to design processors that are capable of executing instructions from two or more instructions threads concurrently. Since instructions from different threads are independent, concurrent execution of two or more instruction threads increases instruction throughput.
A variety of designs have been implemented to support concurrent execution of multiple threads in a single processor package. For example, multi-core processors include multiple execution cores on a single processor chip. Each execution core can be allocated to a different instruction thread, although various resources may be shared to save die area or to allow some communication among the executing threads. Multiple processor chips may also be incorporated in a multi-chip module that provides a single interface to the rest of the system.
Multi-threaded processors include resources to manage the execution of multiple instructions threads on a single execution core. Thread management units provide on-chip storage of state data for multiple threads and update the data as instructions from different threads are processed by the shared core.
A coarse-grained multi-threaded processor executes instructions from only one thread at a time, but on-chip storage of state data for multiple threads reduces the overhead associated with switching instruction execution between the different threads (context switches). Thread switching may be triggered when the currently executing thread encounters a long latency event (Switch-On-Event Multi-Threading or SOEMT).
A fine-grained multi-threaded processor allows instructions from the multiple threads to execute concurrently. For example, instructions may be issued from multiple threads on each clock cycle, or instructions may be issued from different threads on different clock cycles. In both cases, instructions from multiple threads may be in-flight in the execution core at the same time.
In general, both multi-threaded processors and multi-core processors allow more than one thread's context to be active in the processor at the same time. For multi-core processors, some or all of the cores maybe multi-threaded. Here, context refers to the registers that store a thread's architectural state for a particular processor architecture, and may include general, control and application registers. The performance benefits of these and other processors that support multiple thread contexts (“multiple-context processors”) depend, in part, on the capacity of these processors to appear as multiple, equivalent logical processors. This equivalency greatly facilitates the balancing of workloads among the logical processors, and it simplifies management of the threads by the operating system. The goal, in effect, is to make a multiple-context processor appear as a symmetric multi-processor (SMP) system.
To increase symmetry among the multiple threads, certain resources are replicated for each logical processor of the multiple-context processor. For example, an interrupt unit is typically associated with each logical processor, to provide an interface between the logical processor and system level resources or shared resources of the multiple-context processor. The interrupt unit determines whether an interrupt is to be handled and provides a pointer to the interrupt handling code if the interrupt is accepted.
One disadvantage of providing an interrupt unit for each logical processor is that interrupts, particularly those associated with resources shared by the logical processors, are often seen by all logical processors. For example, a multiple-context processor may provide a single interrupt pin to maintain package-level compatibility with single-threaded designs. Interrupts asserted on the pin are seen by the interrupt units of all logical processors. A fan failure in the system may trigger such an interrupt. Because of their equivalence, each interrupt unit registers the interrupt and its associated logical processor executes the interrupt-handler. Interrupts generated by shared on-chip resources or received on system or dedicated interrupt buses may be seen and processed in a similar manner. In many cases, the interrupt could have been handled by one of the logical processors, but the symmetric configuration of the logical processors obliges each to execute the interrupt code.
The present invention addresses these and other issues associated with interrupt handling in processors that support concurrent execution of multiple threads.
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Bobholz Scott
Murty Keshav
Auve Glenn A.
Intel Corporation
Shah Ami Patel
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