Mechanism for initiating an implicit write-back in response...

Details Mechanism for initiating an implicit write-back in response... Mechanism for initiating an implicit write-back in response...

2005-02-22

2005-02-22

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S121000, C711S141000

Reexamination Certificate

active

06859864

ABSTRACT:
A method and apparatus are described for providing an implicit write-back in a distributed shared memory environment implementing a snoop based architecture. A requesting node submits a single read request to a snoop based architecture controller switch. The switch recognizes that another node other than the requesting node and the home node for the desired data has a copy of the data. The switch directs the request to the responding node that is not the home node. The responding node, having modified the data, provides a single response back to the switch that causes the switch to both update the data at the home node and answer the requesting node. The updating of the data at the home node is done without receiving an explicit write instruction from the requesting node.

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Paruvachi V. Raja and Subramaniam Ganesan, A Hardware Cache Coherency Scheme For Multiprocessors, IEEE, 1993, pp. 181-184.

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