Mechanism for high bandwidth DMA transfers in a PCI environment

Details Mechanism for high bandwidth DMA transfers in a PCI environment Mechanism for high bandwidth DMA transfers in a PCI environment

1996-06-21

1999-03-16

Sheikh, Ayaz R.

395281, 395282, 395842, 395872, G06F 1300

Patent

active

058840508

ABSTRACT:
A method and apparatus for maximizing the performance of DMA transfers over a PCI.TM. bus are provided which includes a Per-Channel Retry count, Double Buffer Management, Wait Enable functionality, Back Up register functionality, Gather/Scatter mapping, a method for minimization of PIO writes, Read Semaphore functionality, a method for servicing of DMA transfers during FMU latency periods, Valid bit functionality, high and low water thresholds, and re-usable page tables.

REFERENCES:
patent: 5386532 (1995-01-01), Sodos
patent: 5530902 (1996-06-01), McRoberts et al.
patent: 5613162 (1997-03-01), Kabenjian
patent: 5659798 (1997-08-01), Blumrich et al.
patent: 5682483 (1997-10-01), Wu et al.
patent: 5784592 (1998-07-01), Gulick et al.

Affiliated with

Also associated with

Rating

Mechanism for high bandwidth DMA transfers in a PCI environment does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Mechanism for high bandwidth DMA transfers in a PCI environment, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Mechanism for high bandwidth DMA transfers in a PCI environment will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-825178