Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
2006-02-10
2009-10-27
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Branching
Reexamination Certificate
active
07610474
ABSTRACT:
A technique maintains return address stack (RAS) content and alignment of a RAS top-of-stack (TOS) pointer upon detection of a tail-call elimination of a return-type instruction. In at least one embodiment of the invention, an apparatus includes a processor pipeline and at least a first return address stack for maintaining a stack of return addresses associated with instruction flow at a first stage of the processor pipeline. The processor pipeline is configured to maintain the first return address stack unchanged in response to detection of a tail-call elimination sequence of one or more instructions associated with a first call-type instruction encountered by the first stage. The processor pipeline is configured to push a return address associated with the first call-type instruction onto the first return address stack otherwise.
REFERENCES:
patent: 5561775 (1996-10-01), Kurosawa et al.
patent: 5935238 (1999-08-01), Talcott et al.
patent: 5949996 (1999-09-01), Atsushi
patent: 5964868 (1999-10-01), Gochman et al.
patent: 5964869 (1999-10-01), Talcott et al.
patent: 6035118 (2000-03-01), Lauterbach et al.
patent: 6101326 (2000-08-01), Mattson, Jr.
patent: 6314514 (2001-11-01), McDonald
patent: 6374350 (2002-04-01), D'Sa et al.
patent: 6625719 (2003-09-01), Leach et al.
patent: 6898699 (2005-05-01), Jourdan et al.
patent: 7130972 (2006-10-01), Yamamoto et al.
patent: 2003/0131220 (2003-07-01), Hummel et al.
patent: 2007/0061555 (2007-03-01), St. Clair et al.
Skadron et al. “Improving Prediction for Procedure Returns with Return-Address-Stack Repair Mechanisms” Proceedings of the 31st Annual ACM/IEEE International Symposium on Microarchitecture. IEEE Comp. Soc., Los Almitos, CA, Nov. 30, 1998, pp. 259-271. (XP000871947) .
Hennessy, John, Patterson, David. “Computer Architecture: A Quatitative Approach” Morgan Kaufmann, May 2002, pp. A-22 to A-29.
Hennessy, John L. and Patterson, David A.,Computer Architecture A Quantitative Approach,Third Edition, 2003, pp. 224-240, Morgan Kaufman Publishers, USA.
Desmet, Veerle et al., “Correct Alignment of a Return-Address-Stack after Call and Return Mispredictions”,Proceedings of the 4thWorkshop on Duplicating, Deconstructing, and Debunking, held in Conjunction with the 32ndInternational Symposium on Computer Architecture,2005, pp. 25-33.
Return-Address Stack, http://www.usenix.org/events/sec01/full—papers/frantzen/frantzen—html
ode 11.html, 2 pp.
Caprioli Paul
Chaudhry Shailender
Yip Sherman H.
Chan Eddie P
Gunnison Forrest
Gunnison McKay & Hodgson, L.L.P.
Petranek Jacob
Sun Microsystems Inc.
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