Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-12-13
2005-12-13
Sparks, Donald (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S146000, C711S210000, C707S793000
Reexamination Certificate
active
06976129
ABSTRACT:
A method and apparatus for a mechanism for handling i/o transactions with known transaction length to coherent memory in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a request for a current copy of a data line. The method further includes finding the data line within a cache-coherent multi-node system. The method also includes copying the data line without disturbing a state associated with the data line. The method also includes providing a copy of the data line in response to the request. The method also includes determining if the data line is a last data line of a transaction based on a known transaction length of the transaction.
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Jim Handy, The Cache Memory Book, 1998, Academic Press, Second Edition, pp 157.
Jim Handy, The Cache Memory Book, 1998, Academic Press, Second Edition, pp 156-157.
Creta Kenneth C.
Khare Manoj
Kumar Akhilesh
Looi Lily P.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Sparks Donald
Truong Bao Q
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