Mechanism for handling explicit writeback in a cache...

Details Mechanism for handling explicit writeback in a cache... Mechanism for handling explicit writeback in a cache...

2007-01-23

2007-01-23

Vital, Pierre M (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C711S141000, C711S150000, C711S168000

Reexamination Certificate

active

10896151

ABSTRACT:
A method and apparatus for a mechanism for handling explicit writeback in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a read request relating to a first line of data in a coherent memory system. The method further includes receiving a write request relating to the first line of data at about the same time as the read request is received. The method further includes detecting that the read request and the write request both relate to the first line. The method also includes determining which request of the read and write request should proceed first. Additionally, the method includes completing the request of the read and write request which should proceed first.

REFERENCES:
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patent: 5987571 (1999-11-01), Shibata et al.
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patent: 6145062 (2000-11-01), Chittor et al.
patent: 6256713 (2001-07-01), Audityan et al.
patent: 6636949 (2003-10-01), Barroso et al.

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